Why IC Design Safety Nets Have Limits


Experts at the Table: Semiconductor Engineering sat down to discuss different responsibilities in design teams and future changes in tools with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager at Siemens EDA; Dirk Seynhaeve, vice president of business development at Sigasi; Simon Davidmann, formerly... » read more

Chip Design Digs Deeper Into AI


Growing demand for blazing fast and extremely dense multi-chiplet systems are pushing chip design deeper into AI, which increasingly is viewed as the best solution for sifting through scores of possible configurations, constraints, and variables in the least amount of time. This shift has broad implications for the future of chip design. In the past, collaborations typically involved the chi... » read more

RISC-V Heralds New Era Of Cooperation


RISC-V is paving the way for open source to become accepted within the hardware community, creating a level of industry collaboration never seen in the past, while revitalizing the connection between academia and industry. The big question is whether this arrangement is just a placeholder while the industry re-learns how to develop processors, or whether this processor architecture is someth... » read more

AI For Data Management


Data management is becoming a significant new challenge for the chip industry, as well as a brand new opportunity, as the amount of data collected at every step of design through manufacturing continues to grow. Exacerbating the problem is the rising complexity of designs, many of which are highly customized and domain-specific at the leading edge, as well as increasing demands for reliabili... » read more

Trouble Ahead For IC Verification


Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

Integration Hurdles For Analog And RF In Next-Gen Packages


A rapid increase in wireless connectivity and more sensors, coupled with a shift away from monolithic SoCs toward heterogeneous integration, is driving up the amount of analog/RF content in systems and changing the dynamics within a package. Since the early 2000s, the majority of chips used at the most advanced nodes were systems-on-chip (SoCs). All features had to fit into a single planar S... » read more

Reducing Risk In The Semiconductor Supply Chain


Companies that were hit with chip shortages during the pandemic are changing their strategies to prevent future problems, deploying a combination of supply chain mapping, second sourcing, and digital transformation. Those shortages caused a $200 billion loss for automotive manufacturers, and the disruptions were far more widespread, in many cases lasting for years. Companies of all sorts wer... » read more

Sidestepping Lithography In Chip Manufacturing


Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Veterans Could Close The Semi Industry’s Workforce Gap


Veterans are beginning to form a valuable talent pool for advanced manufacturing and chip-sector positions, helping to fill the current and projected future gap in qualified workers as new fabs come online, and adding discipline and skills that are difficult to find otherwise. The job opportunities are many, and so are the possible job paths. In some cases, veterans are looking to make a qui... » read more

Chip Aging Becoming Key Factor In Data Center Economics


Chip aging is becoming a much bigger concern inside of data centers, where it can impact server uptime, utilization rates, and the amount of energy needed to drive signals and cool entire server racks. Aging in chips is the result of both higher logic utilization and increasing transistor density. This is problematic for data centers, in general, but especially for AI chips where digital log... » read more

← Older posts Newer posts →