Balancing Training, Quantization, And Hardware Integration In NPUs


Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu... » read more

Every Atom Now Counts In Advanced Chip Manufacturing


Artificial-intelligence workloads are pushing semiconductor design to a point where traditional scaling strategies are running out of room. Performance improvements that once came from shrinking transistors now depend increasingly on how devices are stacked, interconnected, and isolated. Transistor scaling still matters, but advanced device architectures no longer can accommodate the power dens... » read more

An Explosion In Interconnect Complexity


For decades, electronics offered two levels of routing structure to manage signals that originate or terminate in an integrated circuit. Recently, that number has risen to five, and while it adds far more flexibility for structuring electronic equipment, it also brings greater complexity and ratchets up the number of design decisions needed to complete a project. This transition has been evo... » read more

Oxides Bring Low Leakage Transistors To Leading-Edge Memories


AI workloads need to position more memory that uses less power in ever-closer proximity to computational logic. That overriding imperative is driving new memory designs and new materials exploration across a wide range of applications, including cache memory, working memory, as well as a new category, non-volatile memory used for direct computation. The largest of these, by volume, is workin... » read more

Addressing Critical Tradeoffs In NPU Design


Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven W... » read more

Startup Funding: Q4 2025


The promise of AI dominated the last quarter of 2025. Investors were eager to claim stakes in both brand-new startups and more established companies developing AI-specific hardware, primarily for data centers, with over $1 billion alone flowing into the sector. The largest round of the quarter went to a new entrant aiming to fundamentally change how AI compute is performed, while two in-memory ... » read more

How And Why To Optimize NPUs


Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones.  Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven... » read more

Liquid Cooling Gains Traction In Data Centers


All electronics generate heat, and that heat must be removed to ensure those electronics don’t overheat. Moving air has been the predominant approach for decades, with liquid cooling limited to particularly intense computing workloads, largely in the supercomputing domain. With the rise in AI, data-center power density has grown to the point where liquid cooling is now seeing a larger buil... » read more

Will 2026 Be Dominated By AI?


Many opportunities and problems became highly interlinked in 2025, fueled by the historic growth in everything AI. But how close are we coming to breaking points, and what are people doing to mitigate them? That is the story that will unfold this year. AI's penetration into an increasing number of workloads is placing almost quadratic demands on compute, memory, interconnect, and the archite... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies


Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

← Older posts Newer posts →