Tool And Methodology Changes Coming In Fab And Package Automation

Experts at the table: Semiconductor Engineering sat down to discuss what’s changing in semiconductor fabs and packaging houses with Michael Lowman, senior product marketing manager for Data Analytics at Cohu; Aftkhar Aslam, CEO at yieldWerx, Woo Young Han, product marketing director at Onto Innovation; and Lihong Cao, senior director of engineering and technical marketing for ASE. What follows are excerpts of that discussion. To view part one of this discussion, click here.

L-R: Cohu’s Lowman, YieldWerx’s Aslam, Onto’s Han, and ASE’s Cao

SE: As process windows shrink, what types of in-line metrology and inspection are required to identify issues early enough that automation can prevent scrap or costly rework or retest?

Han: With all this advanced packaging bonding, a lot of these require wafers to be thinned down. These days we have HBM wafers getting thinned down to 50 microns. Just as a comparison, Scotch tape is 60 to 70 microns thick. When you have a wafer that’s thinner than Scotch tape, you know how fragile that could be. There can be a lot of cracks. With bonding, voids are a very common, high-value challenge for all our customers.

Cao: We’ve invested heavily in new inspection tools, both in-line and IFA. With small features and fine RDL layers, thin wafers might easily cause die cracking. The RDLs, because of stress and warpage, can cause very fine cracking and delamination at interfaces. We stack up many layers for 2.5D and fan-out — we do fan-out with embedded silicon. This is a multiple interface stack-up among different material interfaces, so die cracking or delamination is very critical. Those are not easy to find in-line. Sometimes they can be found after final test or reliability test, and those can cause issues and yield loss. That’s why fine-feature inspection, especially with very fine pitch — even though 3D is less than 10 microns — in fan-out we also see from 55 microns down to 45, and right now we see 35 microns for the bump pitch, for micro bump pitch. Those very small bump pitches require very high-resolution inspection tools.

Optical is already limited. Sensitivity is not enough, and resolution-wise is not enough. We need to use high-resolution 2D and 3D inspection for optical. Definitely, IR — recently IR imaging has become very helpful for inspection of embedded defects like die cracking or die chipping. We also found 3D X-ray and nanoscale X-ray very useful. Right now, 3D X-ray resolution can be sub-micron — less than 500 nanometers, 0.5. Usually people claim 1 micron, and IR imaging resolution is 1 micron. We need high resolution for inspection, but throughput is a bottleneck. That’s the challenge. Also, some tools cannot be used in-line, because in-line we have to weigh throughput. We can use them in the lab inside, but in-line we still need tool suppliers to help us improve the resolution with higher throughput.

Lowman: We certainly have challenges, but we have a pretty good in-line solution for microcracks in particular. Microcracks are particularly difficult to detect, and also sensitive to false rejects, so you end up with a yield hit. More and more customers are moving toward an AI kind of inspection solution, where you look at the signature of the crack as opposed to just some kind of light-level analysis. We do see a nice trend moving in that direction. That’s the most in-my-face trend that I’m observing.

Aslam: From a software application perspective, Michael, Lihong, and Woo Young painted a very nice picture of the challenges — the types of defects like microcracks, the underfills, stress-induced warpage. Those are all key failure characteristics that induce what we call subtle defects or latent defects or nuisance defects. Where we come into the picture is that all these images are being captured. It doesn’t matter if it’s an IR thermal imaging tool or an advanced scatterometry tool. The challenge is now using AI/ML to teach or generate the models and say, ‘When you see an image of this type, this is the root cause of that image,’ and being able to trace it back to what the impact is going to be on electrical tests or final test outcomes when you go into package form. Then really ‘Pareto-ing’ them for customers and saying, ‘The images you’ve given us, we’ve run them through our AI/ML models. Here is the Pareto of problems and the root cause and the potential impact to yield. Which ones do you want to tackle first?’ Not every problem can be addressed, but that’s where our automation comes into play — taking the data, analyzing, modeling, Pareto-ing, and then saying, ‘Go fix these issues. This is what your potential yield impact is going to be.’

SE: How do you see digital twins impacting these challenges? Do they improve the ability to see things as they’re coming, to analyze what might be a problem and improve that whole inspection process?

Cao: Yes, definitely. It helps a lot. We use digital twins, and we have a bigger scope. We want to link everything together, learning from the process, from the defect, from yield learning, and from reliability. In-line, we use machine learning for pattern recognition, and we document and analyze the results with AI. The volume of data we generate is substantial, which makes it well-suited for applying digital twins. We’re still in the stage of linking and collecting data and building the model for full digital twin implementation, but we already use digital twins in design, modifying the design based on what we learn. The machine learning and pattern-recognition capabilities are being applied in specific process steps today.

We also collaborate with Taiwan universities and research institutes, and even universities in the U.S. We build up the models based on the data size we have and based on defect types. For example, voiding and delamination can be easily recognized. We’ve already applied machine learning, and it really enhanced the yield improvement. We also use this and apply it to other customers, so it’s shortening the time and the yield learning path. You can see very fast results right now due to the assistance from machine learning or digital twins.

This is only one portion of the process. A lot of defects can be captured during reliability, as well. We also find that test coverage is becoming more and more blurred. Before, with monolithic simple packages, it was easier — maybe 100% or 98% test coverage could capture the majority of defects. But right now, we see multiple-chiplet integration and complicated package structures, and test coverage from wafer test, from system-level test, from final test, is getting weaker and weaker. That’s why we need to use digital twins to capture defects, to assist in the test and capture defects at an earlier stage. That’s one thing. Combined with reliability, we collect data, and we found that’s very helpful for improving yield in general and assisting in the test and in the process.

Lowman: This is certainly a hot topic. In the last year or so, it’s really cranked up. From our standpoint, we have a digital twin platform, which is a great way to be tool-agnostic. You can start to look at a wider set of data or processes, then attack whatever problem you decide to go after. Has it been adopted? I’m not seeing it firsthand. I do believe it’s a path forward. We have a lot of ideas about how it can be utilized for predictive maintenance and other applications, but it’s more from a tool-agnostic approach. Then, of course, you can scale it to find yield problems, but you have to start getting that data from multiple sources in order to make that happen.

One interesting trend is that test program development is now being encouraged on a digital twin or some kind of simulation tool, which seems to be gaining some momentum. That sounds similar to what you were just mentioning. This can save the use of the test cell to vet out your process and saves time and utilization on the equipment.

Aslam: If you’re a design engineer and you’re selecting your IP, you want to be able to say, ‘If I select this IP, I want to see actual results that show this IP has been used in a full-fledged product and it’s running in production. A second aspect is, in the digital twin, why are we just thinking about design when we can think about, ‘Where am I designing my probe cards? How am I doing DFT (design for test)?’ Add to that design for manufacturing. When you do your simulation within tools like PLM, you’re able to simulate manufacturing processes, you’re able to simulate testability of the product, all the way down to a component level. It’s not just about a digital twin of equipment. We want to be able to start the digital twin of manufacturing, assembly, and design. With that said, this thread comes into play: How can I take real-life data and marry it to engineering BOMs that are the heart of a digital twin? As an engineer, you can then use powerful simulation tools, and with the advancements that AI is making now, you can theoretically come up with very high predictability on where your problems are going to be in manufacturing, assembly, and test, and also the problems you see in peripherals like load boards, probe cards, actual test equipment itself. That’s where we’re partnering up with the PLM vendors, saying we can provide the back-end data part of that closed loop all the way to design. If you’re a manufacturing engineer or a test and product engineer or a design engineer, all three groups have to collaborate to create those digital twins. Our platform enables that common thread, the common language to drive digital twins.

Han: From our side, at a given high-volume manufacturing factory, there could be as many as 100 inspection tools of the same kind. They’re asking us for a better way to really manage and match all these tools. That’s another area we’re working on with our customers. With so many tools in the same fab, how do we ensure they are working and matched?

SE: Looking out over the next three to five years, are there automation technologies that you expect to have a bigger impact on advanced packaging? Is anything either missing and needed, or in development now that can have a profound impact?

Lowman: Thermal management is a big aspect of what we can provide to the equation from an automation perspective, and that’s going to be a huge impact. Just using machine learning and any type of environment where you’re actually becoming more predictive with your forecasting of a problem, and turning unscheduled downtime into planned downtime — all those things associated with the lights-out factory are what’s required. The back end is loaded with customers who are increasing their automation scope.  Many are building factories in Southeast Asia to expand their capabilities, and most of them aim to be fully automated. Automation is driving a lot of these requirements. It’s not just advanced packaging, but automation itself.

Aslam: We see it as a combination. We see it as smarter tools, but also smarter analytics. There’s not one magic instrument that’s going to solve all these problems. On the hardware side, we’re looking at better tools with higher resolution, higher throughput — being able to X-ray or look for hybrid bonding issues or finer pitch, better in-situ defect monitoring or warpage monitoring — all the stuff that we have mentioned already. But equally important is going to be, what are we actually monitoring on-die? What are the on-die parameters that we are monitoring? What are the KPIs? Is it telemetry? Especially as products become more complex and we go into the whole chiplet era. What we see already happening is that there are no standards, per se, in the industry that say how to collect data. We can collect data at the die level. I have a die, my x,y is this, this is the location on the wafer, but what about when I want to collect chiplet-level data?

If you think about photonics products and quantum compute products, where we’re now talking about optical ports and we have layers and macros and slices that interconnect chiplet to chiplet, we don’t have those standards anywhere defined. Everybody’s in the Wild West coming up with their own formats and standards. That’s going to be one area where we need to bring some kind of standardization to the madness. Then we can fuse all this data together. We can apply AI and ML, but you’re not applying AI/ML on just garbage. From there we can come up with actions. Those actions could be multivariate power averaging tests, they could be adaptive probe, actionable items that we can then take back and say, ‘With this data and these AI analytics have been performed, these are the actions we can take in the fab, these are the actions we can take back into design.’ That’s going to be a real focus area for the next three to five years.

Han: All the tier-one customers that we serve have a very common request, and that is they prefer not to make recipes. They want recipe-less inspection or a universal recipe. With AI and machine learning evolving, they’re all asking, ‘Can we somehow utilize all this machine learning so that our engineers don’t need to spend time making recipes?’ We’re investing heavily in this area, pushing toward recipe-less inspection or a universal recipe.

Cao: What will be needed are definitely faster, higher-resolution, higher-detection capabilities with throughput. That is the key with high yield. In the next three to five years, that’s our target. To achieve that, we really need automation. We need automated integration of multiple-skill metrology. This is the maturity case. For example, we can integrate optical microscopy, different types of solutions, X-ray, acoustic, AFM. Those we hope can really detect multiple defects at one time. That’s one thing. Another thing is it’s a very tough task that cannot be done manually. That’s why we want to use AI, especially an AI inference engine installed in these inspection tools to help us. Another one people talk about is digital twins, because digital twin is a huge project. If we use partially digital twins to combine all this data and provide the physics-aware in advance from design, from process, before we get to final test and reliability, if we can fix the issue upfront, that’s also what we want to look into in the next three to five years. We’re also looking for a hybrid ecosystem that includes the supply chain. If we can standardize from upstream to downstream — in data formats, in process design, and from a test perspective — that level of standardization across the ecosystem will help ASE over the next three to five years.