Auto Chip Test Issues Grow


By Jeff Dorsch & Ed Sperling Semiconductor suppliers are flocking to the automotive chip market to gain share in fitting out the connected car and the autonomous vehicle. But before those chips are sold to automotive manufacturers and Tier 1 suppliers, they must be tested and certified to meet stringent industry standards. This is no ordinary testing, though. Assisted and autonomous v... » read more

Getting Serious About Chiplets


Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications. The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM's packaging schem... » read more

Reshaping Automotive Design


The entire automotive ecosystem is being reshaped by vehicle electrification, assisted and autonomous driving, and the connectivity needed to make it all work. So far, it's not clear just how smoothly this will all come together. In this redefined world, electronics and software will provide differentiation rather than mechanical engineering and possibly even brand name, creating change on a... » read more

Who’s Responsible For Security?


Semiconductor Engineering sat down to discuss security issues and how to fix them with Mark Schaeffer, senior product marketing manager for secure solutions at Renesas Electronics; Haydn Povey, CTO of Secure Thingz; Marc Canel, vice president of security systems and technologies at [getentity id="22186" comment="Arm"]; Richard Hayton, CTO of Trustonic; Anders Holmberg, director of corporate dev... » read more

Mixed-Signal Issues Worse At 10/7nm


Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

Reflection On 2017: Design And EDA


People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Reflections On 2017: Manufacturing And Markets


People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts that looks at the pred... » read more

Foundry Challenges in 2018


The silicon foundry business is expected to see steady growth in 2018, but that growth will come with several challenges. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC are migrating from the 16nm/14nm to the 10nm/7nm logic nodes. Intel already has encountered some difficulties, as the chip giant recently pushed out the volume ramp of its new 10nm process from the second half ... » read more

Is Verification Falling Behind?


Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

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