category: Top Stories

category: Auto, Security & Edge AI

Options Grow For Standardizing Data Movement And Sharing Resources
By Ed Sperling - 20 May, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh Choudhary, senior principal engineer at Intel; Siamak Tavallaei, senior principal engineer at Samsung SSI; and Mohsen Asad, senior director of technology at Credo. What follows are excerpts of a disc... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Chiplets Need A New Workflow
By Ann Mutschler - 14 May, 2026 - Comments: 0

Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out. ... » read more

Gates Add Functionality, But Wires Create Problems
By Brian Bailey - 14 May, 2026 - Comments: 0

Key takeaways: While transistors see continuous improvement, wires keep getting worse because of the smaller geometries and larger chip sizes. There are limited ways to avoid such problems, but the biggest impact will come from floorplanning. Analysis today is not adequate. New developments, such as backside power and 3D integration, provide temporary relief but new materials are a d... » read more

AI Accelerator Testing Depends On DFT Innovations
By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

Smart Test Collides With The Data Chain
By Gregory Haley - 12 May, 2026 - Comments: 0

Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield
By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

Building AI Without Guardrails
By Ann Mutschler - 07 May, 2026 - Comments: 0

Key Takeaways: AI governance is broadly recognized as essential, but today it remains fragmented, largely aspirational, and lacking enforceable mechanisms for accountability, runtime assurance, and global interoperability. Because AI innovation is advancing too quickly for governments or standards bodies to keep pace, practical AI governance is most likely to emerge first from high‑ri... » read more

Next-Gen Batteries Require Impedance Data And Active Balancing
By Liz Allan - 07 May, 2026 - Comments: 0

Key Takeaways Electric vehicles and energy storage systems using LFP batteries require more sophisticated diagnostic methods because they exhibit very flat cell voltages across various charge levels, making it harder to estimate usable energy. Battery management systems are leveraging new components, AI/ML, digital twins, and other techniques to get more accurate, real-time data, includ... » read more

Using AI To Monitor Dashboards In Chips And Systems
By Ed Sperling - 06 May, 2026 - Comments: 0

Key Takeaways: New types of dashboards are being used in conjunction with AI to make sense of large quantities of data. These dashboards can be used to quickly identify and fix power and heat-related problems, such as hotspots or voltage droop. Future dashboards will likely be much more customizable for different users or applications. Chipmakers are starting to use AI to ma... » read more

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