Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Closing The Loop On Power Optimization


[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Analog’s Unfair Disadvantage


We live in an analog world, and yet digital has become the technology of choice. Mixed-signal solutions that used to contain significant amounts of analog, with just a small amount of digital signal processing, have migrated into systems where the analog to digital conversion happens at the very first opportunity. There are several reasons for this, and some of them build upon themselves. [g... » read more

2.5D, Fan-Out Inspection Issues Grow


As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, [getkc id="82" kc_name="2.5D"] and [getkc id="42" kc_name="3D-IC"], along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moo... » read more

Wireless Test: Too Many Protocols


Testing wireless communications is getting far more difficult as more markets begin adding wireless communications and standards groups push to improve the speed, power and security of existing protocols. There is already a long list of protocols, and it's growing further as new communications technologies are added into the mix. With the addition of 5G, the new 802.11ax standard, and other ... » read more

Wirebond Technology Rolls On


Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types. Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconducto... » read more

Intel Inside The Package


Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

IIoT Grows, But So Do Risks


By Jeff Dorsch & Ed Sperling After years of fitful progress, [getkc id="78" kc_name="Industrial Internet of Things"] technology is gaining adoption on the factory floor, in the electrical power grid, and other areas that could do with greater amounts of data analysis and insights from a connected ecosystem. AT&T, General Electric, IBM, Verizon Communications, and other large ... » read more

Autonomous Cars Drive New Software


Autonomous driving and other advanced features will require much more sophisticated software than what is used in vehicles today. To make this all work will require complex algorithms as well as co-designed hardware, which can make real-time decisions to avoid accidents and adjust to changing road conditions. Automobiles already take advantage of sophisticated software executed by a variety ... » read more

Verification And The IoT


Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

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