category: Top Stories

category: IoT, Security & Automotive

Can IP Integration Be Automated?
By Ann Mutschler - 24 Sep, 2015 - Comments: 1

What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

ROI Not There Yet For SysML
By Ann Mutschler - 24 Sep, 2015 - Comments: 3

At some point down the road in the realm of system-level design, the Systems Modeling Language (SysML) dialect of the Unified Modeling Language (UML) standard may drive into semiconductor design. So far, however, a return on investment has not been established for its use. SysML is defined as a general-purpose visual modeling language for systems engineering applications, and it supports the... » read more

The Price Of Consolidation
By Ed Sperling - 24 Sep, 2015 - Comments: 0

Consolidation is causing far-reaching changes across the global semiconductor ecosystem due to the size of companies being bought and the dearth of startups to replenish those being acquired. Coupled with the rising cost and difficulty of shrinking features down to advanced process nodes—many argue that is the largest driver of consolidation—the market dynamics for who's buying IP, EDA t... » read more

ESL: 20 Years Old, 10 To Go
By Brian Bailey - 23 Sep, 2015 - Comments: 2

It is a common perception that the rate of technology adoption accelerates. In 1873, the telephone was invented and, after 46 years, it had been adopted by one-quarter of the U.S. population. Television, invented in 1926 took 26 years. The PC in 1975 took just 16 years. It took only 7 years after the introduction of the Internet in 1991 before it was seeing significant levels of adoption. So... » read more

Power Estimation: Early Warning System Or False Alarm?
By Brian Bailey - 22 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kulkarni, senior vice president and general m... » read more

Chasing After Quantum Dots
By Mark LaPedus - 21 Sep, 2015 - Comments: 2

In the 1980s, researchers stumbled upon a tiny particle or nanocrystal with unique electrical properties. These mysterious nanocrystals, which are based on semiconductor materials, were later named quantum dots. Quantum dots were curiosity items until 2013, when Sony launched the world’s first LCD TV using these inorganic semiconductor nanocrystals. Basically, when inserted into an LCD TV,... » read more

Finding Defects Is Getting Harder
By Mark LaPedus - 17 Sep, 2015 - Comments: 1

Chipmakers are plotting out a strategy to scale the transistor to 10nm and beyond. Migrating to these nodes presents a number of challenges, but one issue is starting to gain more attention in the market—killer defects. Defects have always been problematic in the yield ramp for chip designs, but the ability to find them is becoming more difficult and expensive at each node. And it will be... » read more

Mask Supply Chain Preps For 10nm
By Dylan McGrath - 17 Sep, 2015 - Comments: 0

As the semiconductor industry gears up for the 10nm logic node—now likely to begin in the second half of 2017—the photomask supply chain is preparing to grapple with the associated challenges, including dramatic increases in photomask complexity, write times and data volumes. The 10nm node will require more photomasks per mask set, the ability to print smaller and more complex features, ... » read more

ALD Market Heats Up
By Mark LaPedus - 17 Sep, 2015 - Comments: 1

Amid the shift to 3D NAND, finFETs and other device architectures, the atomic layer deposition (ALD) market is heating up on several fronts. Applied Materials, for example, recently moved to shakeup the landscape by rolling out a new, high-throughput ALD tool. Generally, [getkc id="250" kc_name="ALD"] is a process that deposits materials layer-by-layer at the atomic level, enabling thin and ... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

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