What Scares Chip Engineers About Generative AI


Experts At The Table: LLMs and other generative AI programs are a long way away from being able to design entire chips on their own from scratch, but the emergence of the tech has still raised some genuine concerns. Semiconductor Engineering sat down with a panel of experts, which included Rod Metcalfe, product management group director at Cadence; Syrus Ziai, vice-president of engineering at E... » read more

Linear Pluggable Optics Save Energy In Data Centers


Linear pluggable optics (LPO) is garnering more attention as a way to quickly and efficiently move data in and out of server racks, but a lack of standards for connecting the optical modules is slowing adoption at a time when there is growing pressure to reduce power in data centers. LPO is the newest of two approaches to solving the power wall problem in data centers. Co-packaged optics (CP... » read more

Interconnects Approach Tipping Point


As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

Memory Wall Problem Grows With LLMs


The growing imbalance between the amount of data that needs to be processed to train large language models (LLMs) and the inability to move that data back and forth fast enough between memories and processors has set off a massive global search for a better and more energy- and cost-efficient solution. Much of this is evident in the numbers. The GPU market is forecast to reach $190 billion in ... » read more

What’s Next In Advanced Packaging?


Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC progress and issues, photonics, and tradeoffs with different interposers and bridge technologies, with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What fo... » read more

ADAS Adds Complexity To Automotive Sensor Fusion


Sensor fusion is becoming increasingly popular and more complex in automotive designs, integrating multiple types of sensors into a single chip or package and intelligently routing data to wherever it is needed. The primary goal is to bring together information from cameras, radar, lidar, and other sensors in order to provide a detailed view of what's happening inside and outside of a vehicl... » read more

Signal Integrity Plays Increasingly Critical Role In Chiplet Design


Maintaining the quality and reliability of electrical signals as they travel through interconnects is proving to be much more challenging with chiplets and advanced packaging than in monolithic SoCs and PCBs. Signal integrity is a fundamental requirement for all chips and systems, but it becomes more difficult with chiplets due to reflections, loss, crosstalk, process variation, and various ... » read more

Normalization Keeps AI Numbers In Check


AI training and inference are all about running data through models — typically to make some kind of decision. But the paths that the calculations take aren’t always straightforward, and as a model processes its inputs, those calculations may go astray. Normalization is a process that can keep data in bounds, improving both training and inference. Foregoing normalization can result in at... » read more

What Exactly Is Multi-Physics?


Multi-physics is the new buzzword in semiconductor design and analysis, but the fuzziness of the term is a reflection of just how many new and existing problems need to be addressed simultaneously in the design flow with advanced nodes and packaging. This disaggregation of planar SoCs and the inclusion of more processing elements, memories, interconnects, and passives inside a package has cr... » read more

Optimizing DFT With AI And BiST


Experts at the Table: Semiconductor Engineering sat down to explore how AI impacts design for testability, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; Dave Armstrong, principal test strategist at Advantest; and Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA. Wh... » read more

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