Thermal Integrity Challenges Grow In 2.5D


Thermal integrity is becoming much harder to predict accurately in 2.5D and 3D-IC, creating a cascade of issues that can affect everything from how a system behaves to reliability in the field. Over the past decade, silicon interposer technology has evolved from a simple interconnect into a critical enabler for heterogeneous integration. Interposers today may contain tens of dies or chiplets... » read more

What Designers Need To Know About GAA


While only 12 years old, finFETs are reaching the end of the line. They are being supplanted by gate-all-around (GAA), starting at 3nm [1], which is expected to have a significant impact on how chips are designed. GAAs come in two main flavors today — nanosheets and nanowires. There is much confusion about nanosheets, and the difference between nanosheets and nanowires. The industry still ... » read more

Transitioning To Photonics


Silicon photonics is undergoing a resurgence as traditional approaches for reducing power and heat become more difficult and expensive, opening the door to a whole new set of technological challenges and driving up demand for a skill set that is in short supply today. From a technology standpoint, photonics is extremely complex. Signals drift, they are modulated with heat, and structures lik... » read more

RISC-V Driving New Verification Concepts


Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

What Data Center Chipmakers Can Learn From Automotive


Automotive OEMs are demanding their semiconductor suppliers achieve a nearly unmeasurable target of 10 defective parts per billion (DPPB). Whether this is realistic remains to be seen, but systems companies are looking to emulate that level of quality for their data center SoCs. Building to that quality level is more expensive up front, although ultimately it can save costs versus having to ... » read more

Challenges In Photonics Testing


Photonics is poised for significant growth due a rapid increase in data volumes and the need to move that data quickly and with minimal heat. But to reach its full potential photonics will have to overcome several production hurdles. The biggest challenge today involves alignment. While the industry is poised to produce billions of units, it still relies on testing practices that don't scale. ... » read more

Challenges Grow For CD-SEMs At 5nm And Beyond


CD-SEM, the workhorse metrology tool used by fabs for process control, is facing big challenges at 5nm and below. Traditionally, CD-SEM imaging has relied on a limited number of image frames for averaging, which is necessary both to maintain throughput speeds and to minimize sample damage from the electron beam itself. As dimensions get smaller, these limitations result in higher levels of n... » read more

Chiplet Security Risks Underestimated


The semiconductor ecosystem is abuzz with the promise of chiplets, but there is far less attention being paid to security in those chiplets or the heterogeneous systems into which they will be integrated. Disaggregating SoCs into chiplets significantly alters the cybersecurity threat landscape. Unlike a monolithic multi-function chip, which usually is manufactured using the same process tech... » read more

Growing Challenges For Increasingly Connected Vehicles


Automobiles will become increasingly connected over the next decade, but that connectivity will come at a price in terms of dollars, security, and constantly changing technology. Connectivity involves all parts of a vehicle. It includes everything from autonomous driving to in-cabin monitoring and connected infotainment. And it encompasses external sensors, IoT, V2X, over-the-air communicati... » read more

What’s Required To Secure Chips


Experts at the Table: Semiconductor Engineering sat down to talk about how to verify that a semiconductor design will be secure, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker Verification. ... » read more

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