category: Power Down

category: IoT, Security & Automotive

A Strategy For Designing For Power With FinFETs
By Anand Iyer - 11 Sep, 2015 - Comments: 0

Recently Qualcomm announced their new SnapDragon processor 820, which was designed using finFET technology. They showed some amazing results, such as 2X improvement in performance and 2X improvement in power compared to 28nm designs. Previously, when ARM announced their A72 processors in finFET, they too had claimed 3.5X improvement in power compared to 28nm designs. But can designers expect... » read more

Doing More With RTL Power Analysis: Smart Synthesis Architecture
By Anand Iyer - 13 Aug, 2015 - Comments: 0

Traditionally RTL power analysis has been used to understand the design power consumption so that package and power supply designs can start, and designers can then fix any power regression violations in subsequent design iterations. However, migration to finFET processes is causing designers to look at RTL power analysis differently at advanced nodes. FinFET processes have largely addressed... » read more

Microarchitecture Design For Low Power
By Anand Iyer - 14 May, 2015 - Comments: 0

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce dynamic power in the design. In our last blog, we looked at dynamic power wastage due to redundant adders and multipliers and how to gate these operators to save power. We also mentioned a couple of m... » read more

Power Reduction At RTL: Data Gating Adders And Multipliers
By Rob Eccles - 20 Apr, 2015 - Comments: 0

In our previous blog, “Low Power Paradox”, we discussed the implications of the move to FinFET technology. Dynamic power is dominant in finFET designs. Several techniques are available to reduce dynamic power consumption. Microarchitecture changes are one method and they can result in significant power savings. One technique that is frequently used is the data gating of adders and m... » read more

Low Power Paradox
By Anand Iyer - 13 Mar, 2015 - Comments: 0

Power has been an important design challenge for quite some time. Leakage power started to grow in 90nm, and by 65nm it became a severe design issue. We have built many techniques to address leakage, most notably power gating. These techniques are complex and have an impact on the design as a whole. FinFET technologies are seen as a boon to this issue of leakage. There are references that qu... » read more

(Low) Power Predictions 2015
By Anand Iyer - 15 Jan, 2015 - Comments: 1

Happy New Year! As we step into the New Year, lots of exciting things are already underway. First of all, the Internet of Things (IoT) is shaping up in a big way as witnessed at CES last week. Advances in devices that can talk to each other and share information are becoming a reality. Automotive applications, medical devices, industry automation, energy distribution and entertainment are all a... » read more

A Survey Of Our Low Power Blogs In 2014
By Rob Eccles - 12 Dec, 2014 - Comments: 0

Over the past year, we have written a number of blogs on low power IC design. Here at the end of 2014 approaches, let’s look back at what we have discussed Our blogs covered methods to estimate and reduce power consumption in digital ICs. Our recommendation is that you do this early in the design cycle, such as the RTL coding stage, when you can have the most positive impact. In the first... » read more

Memory Gating Power Optimizations
By Rob Eccles - 07 Nov, 2014 - Comments: 0

Saving power in SOCs is challenging. Often there are many memories, which collectively can consume a significant amount of power, compelling designers to make architectural choices to minimize power. These require a fair amount of study and may impact functionality and/or embedded software. Fortunately, memory gating can save power without impacting the architecture or the software. The... » read more

Making Accurate Power Estimates At RTL
By Rob Eccles - 14 Oct, 2014 - Comments: 0

It may seem counterintuitive, but an accurate estimation of power at Register Transfer Level can be made. In this blog, we will learn how it can be done. The main ingredient In order to understand RTL power estimation, let us first consider making the power estimation at gate level. At gate level we have a netlist that contains standard cell instances. These standard cells have been charact... » read more

Low Power Design: RTL Power Analysis
By Anand Iyer - 11 Sep, 2014 - Comments: 0

In last month’s blog, we discussed and compared various power techniques. A quick recap of these power techniques is shown in figure 1. Selecting between them is often quite challenging. These techniques need to be selected during RTL design. At the RTL, designers need a power analysis solution that guides them to the right techniques for their design. In this month’s blog, we will review t... » read more

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