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Creating A Strategy For Power Reduction In ICs


In last month’s blog, various power saving techniques were presented. These different techniques fit into three categories: gross (or coarse-grain) design, fine-grain design, and fine-grain process. In this blog, different techniques will be compared. By understanding the different techniques, it will become clear which ones to use in your design. Fine-grain process techniques For ... » read more

LP SoC Design: Part 2


In my last blog I talked about why designers need to rethink their methodology for low-power design and also introduced gross and fine-grain low power techniques. In this blog I am going to compare and contrast these techniques. Low-power design techniques fall under two categories, gross and fine-grain. Gross techniques are not dependent on the design or the process. Techniques such as powe... » read more

Low-Power SoC Design


Over the last decade, power has become the primary design constraint for all SoC designs. While power reduction started in mobile market segments due to the battery considerations, it quickly has become equally important to powerline applications due to the cooling costs. Today, CPUs define a power constraint called Thermal Design Power (TDP) for the market it operates. One of the definition... » read more

Switching Activity And The Unknown


Switching activity is essential to measuring power in digital circuits, and it is also important for optimizing digital designs. Power can be static, caused by leakage, or dynamic, caused by switching. Switching activity is crucial because dynamic power is, after all, proportional to the switching activity in the design. Definition Switching activity is the measurement of changes of signal ... » read more

With Low-Power Comes Great Responsibility


Recent trends in the consumer electronics market show a demand for short, slim, and light-weight but powerful devices (with the only exception being displays, which are getting larger). Therefore area, timing, and power have all become “critical” to design; whereas in the past, one was prioritized over the others depending on design requirements. However, power is the dominant factor tod... » read more

Verifying Power Optimized Designs Using Sequential Analysis


All power optimization tools can perform combinational optimization, where there is an opportunity to gate a register clock input, based on the combinational logic that is feeding the register’s data input. While this method works well and does not alter the logic behavior at the register, the problem is that it leaves additional power saving opportunities on the table. However, sequential... » read more

Power Optimization Considered


The explosive emergence of hand-held computing and entertainment devices fuels an ever-increasing demand for longer battery life. In fact, 70% of all new hardware development is targeted toward mobile devices. Ancillary to this phenomenon, technology scaling has increased the number of transistors that can be packed per unit area. More and more functionality can be put into electronic devices. ... » read more

Lightening The Information Overload


We live in an age where it’s very easy to suffer from information overload — even when that information leads to better designs. Power optimization tools have been very well received in the market, with almost every major electronics company using these tools and seeing the benefits. Yet, if a power optimization tool shows you everything you can do to improve your design, it’s too much... » read more

Smarter Clock Gating


By Ghulam Nurie With the proliferation of mobile devices, power consumption and battery life have emerged as significant concerns during chip design. There are many different techniques used for power optimization, but of all the different techniques, clock gating is the most popular and widely used technique, according to a blind, anonymous survey emailed to several thousand participants worl... » read more

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