category: Whitepapers

category: IoT, Security & Automotive

Power Delivery Network Verification Coverage
By Ansys - 03 Dec, 2014 - Comments: 0

Power grid verification is a challenge, and there are no industry standards for design teams to follow that will verify the power grid for power and signal integrity issues. In other areas there is typically a verification plan with checks to perform, and when successfully completed, the design is then considered verified to proceed to tape-out. Having high coverage in the power grid’s power... » read more

A Faster, More Accurate Approach For System-Level Performance Verification Of A Wireless RFIC Design
By Cadence - 03 Dec, 2014 - Comments: 0

Wireless RFIC designs are growing more complex, increasing the challenge of verifying system-level performance. Designers are expected to be experts on a variety of ever-changing wireless standards and protocols. They must also contend with time-consuming manual simulation setup and post-processing of the simulation results. This paper discusses how an advanced simulation methodology, involving... » read more

Real-Time Trace: A Better Way To Debug Embedded Applications
By Synopsys - 03 Dec, 2014 - Comments: 0

Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This white paper shows the benefits of debugging with ‘real-time trace’... » read more

A Method To Quickly Assess The Analog Front-End Performance In Communication SoCs
By Synopsys - 19 Nov, 2014 - Comments: 0

This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and oper... » read more

How To Speed Signoff Extraction By 5X With Next-Generation Extraction Tool
By Cadence - 19 Nov, 2014 - Comments: 0

Parasitic extraction, particularly in the digital world, is becoming an increasingly time-consuming process. Not surprising, considering the explosion in interconnect corners, increasing design sizes and number of parasitics, and complex modeling features at advanced nodes, including FinFETs. This paper discusses capabilities you should have in order to overcome parasitic extraction challenges,... » read more

Migrating Consumer Electronics To The Automotive Market With Calibre PERC
By Mentor, a Siemens Business - 19 Nov, 2014 - Comments: 0

Tough reliability standards for electronic automotive safety systems ensure that integrated circuits (ICs) for these systems comply with demanding performance and reliability requirements. However, companies seeking to leverage their consumer-based intellectual property (IP) for use in automotive “infotainment” and “connected car” applications are finding that many of these performance ... » read more

Divide And Conquer: Hierarchical DFT For SoC Designs
By Mentor, a Siemens Business - 13 Nov, 2014 - Comments: 0

Large System on Chip (SoC) designs present many challenges to all design disciplines, including design-for-test (DFT). By taking a divide-and-conquer approach to test, significant savings in tool runtime and memory consumption can be realized. This whitepaper describes the basic components of a hierarchical DFT methodology, the benefits that it provides, and the tool automation that is availabl... » read more

Power And Noise Integrity For Analog / Mixed-Signal Designs
By Ansys - 05 Nov, 2014 - Comments: 0

The convergence of advance process technology, increasing levels of integration, and higher operating frequencies pose considerable challenge to IP designers whose circuits are required to function in variety of conditions. Full-custom and mixed signal circuit designers ensure that their circuits will function by simulating for various operating conditions (PVT, input stimuli, etc). One key asp... » read more

Automated Assertion-Based Verification Methodologies For IP And SoC Development
By Atrenta - 05 Nov, 2014 - Comments: 0

The rapid growth in complexity and size of modern System on Chip devices (SoCs), along with the expense of developing these ICs, has driven the need for design reusability. Today, SoC designs are typically built as a collection of individual IP (Intellectual Property) blocks stitched together with glue logic. These IP can be sourced from multiple design teams, including many 3rd-party teams. So... » read more

Three Challenges Impacting The Efficiency Of PCB Engineering Teams
By Mentor, a Siemens Business - 05 Nov, 2014 - Comments: 0

We live in an era of rapidly accelerating design complexity, with designs often doubling in performance and/or capacity between board revisions. At the same time, we’re seeing a shift in the workforce, particularly in the older design markets of the United States and Europe. Finally, we live in an era where everything’s a system—the days of standalone, single-board projects are gone. Cons... » read more

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