Changes And Challenges

At 130nm, the shift to copper interconnects and 300mm wafer sizes was considered to be the most difficult transition in its long and incredibly efficient history. The next chapter will be even tougher.

It’s not that change is a foreign concept to semiconductor design and manufacturing. In fact, it’s probably the only constant over the past 50 years. But in the past, those changes tended to be confined to individual companies or very narrow parts of the supply chain. It’s now happening across an increasingly complex ecosystem, with changes in one part affecting those in others.

On the ground level, there are very specific problems that need to be addressed by specific market segments. For example, equipment makers are looking at improving the mobility of electrons and new fin materials, while EDA companies are focused on multipatterning rules, test and thermal analysis, along with myriad other things. Move up to 30,000 feet, however, and the view looks completely different. At that level the challenge becomes ecosystem choreography involving all of those changes and more.

To put this in perspective, at 130nm the shifts were in the hands of foundries, which passed down the changes to the EDA vendors and ultimately to the companies that utilized their services. At 14nm, the companies that need to jointly address future issues include EDA companies, foundries, chip makers—IDMs and fabless—materials researchers, equipment makers, packaging houses and IP vendors.

Even the rules of engagement are in flux, which is one of the key reasons why stacked die momentum has fallen apart. If companies cannot sort out liability issues at 20nm and 28nm, it’s only going to get tougher with ultra-thin 14nm logic die packaged with 40nm analog using either TSVs or interposers.

Moreover, each new step is very costly, and the results are uncertain. EUV clearly will play a role in advanced lithography, but most likely not the one that was envisioned before billions of dollars were poured into research. The probable scenario is that it will become one of several lithography approaches used, along with multi-patterning and DSA, rather than the lithography approach. And despite all the ruckus, the jury is still out on 450mm wafers, because there are some doubts about whether enough companies actually will benefit from it to warrant the investment.

Moreover, it’s not just one company that has to agree on the direction these days. It’s an ecosystem of many companies. Even Intel and Samsung can’t afford to go it alone, which is why they have opened their doors to foundry customers and increasingly are purchasing third-party IP. Add in a slew of new materials, process steps and packaging options that need to be tested and re-tested, with complex processes that need to be understood by tools and design teams, and the costs begin to spiral out of control.

The semiconductor industry will solve these issues, of course, one by one. It will even integrate all of these solutions across an increasingly complex supply chain. But at an ecosystem level, those advances will have to become far more measured, be implemented more slowly, and they will require more buy-in from many more players.