KAN for lightweight edge inference; bendable non-silicon RISC-V microprocessor; low-latency, energy-efficiency LLM inference; using both faces of polar semiconductor wafers; low-level SRAM cache 3DIC; formal verification; volatile memristors; 3D multilayer glass structure.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference | Georgia Tech, TSMC and National Tsing Hua University. |
| Bendable non-silicon RISC-V microprocessor | Pragmatic Semiconductor, Qamcom, and Harvard University |
| Breakthrough low-latency, high-energy-efficiency LLM inference performance using NorthPole | IBM Research |
| Using both faces of polar semiconductor wafers for functional devices | Cornell University and Polish Academy of Sciences |
| Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs | imec |
| Analogous Alignments: Digital “Formally” meets Analog | Infineon Technologies |
| VVTEAM: A Compact Behavioral Model for Volatile Memristors | Technion – Israel Institute of Technology |
| Characterizing the Broadband RF Permittivity of 3D-Integrated Layers in a Glass Wafer Stack from 100 MHz to 30 GHz |
NIST |
More Reading
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