Determining the impact of temperature on electrical performance.
When applications become more complex, higher data rates or high frequencies are required. However, with increasing functions, more power dissipation will be generated. Furthermore, temperature is proportional to power dissipation, so electrical performance will also depend on thermal conditions. To determine how temperature impacts power integrity/signal integrity (PI/SI), electrical simulations including package design and printed circuit board (PCB) design were conducted. Using the system block shown in figure 1, each step will be illustrated respectively.
Fig. 1: System block diagram.
Note: all measurements made with and without temperature.
First, package (PKG) and PCB designs were optimized at room temperature by electrical simulation to ensure the subsequent results were not caused by improper designs. Then, the Double Data Rate 5 (DDR5) RAM blocks were evaluated in both package and PCB, and repeated running all electrical simulations listed below. PKG power was set for 3W with 20W for the PCB. Since metal conductivity will change with temperature, the initial temperature was set as 25°C and 85°C, respectively. Simulations were run until power convergence of less than 1% was achieved.
In figure 2, there are two scenarios with the two different initial temperatures of 25°C and 85°C. At the initial temperature of 25°C, the temperature in the PKG and PCB rose to 112°C and 49°C, respectively, and resistance at the DC level increased by around 34% in the package and 8% in the PCB. At an initial temperature of 85°C, temperature in the PKG and PCB rose to 177°C and 165°C, respectively, and resistance at the DC level increased by around 27% in the package and 26% in the PCB. The AC resistance at 1000 MHz in the PKG design had a 15% variation, but there was no significant difference for the inductance and capacitance because the dielectric constant with temperature did not change significantly. In other words, only the resistance in the DC/AC level will increase significantly when the temperature rises. Table 1 summarizes the results of the temperature map.
Fig. 2: IR drop with temperature map.
Table 1: RLC with temperature map.
Next, the difference of the characteristic impedance was evaluated when the temperature rises from different initial temperatures. Material properties, such as metal conductivity, dielectric constant, and loss tangent, change with frequency and temperature variations. However, in figure 3, the trace impedances with different temperatures were almost consistently constant. Exceptions occurred in some segments routed on a bump area or via, which could not follow the impedance-control rule. In Table 2, the variation of Z0 in the PKG design was 1.6%. It was only 1% when temperatures rose from 25°C to 112°C and from 85°C to 177°C. However, in the PCB design, it was almost the same in both instances. Table 2 summarizes the results of the temperature changes on the impedance.
Fig. 3: Characteristic impedance changes with temperature.
Table 2: Z0 with different temperatures.
The S-parameters of DDR5-4000MT/s byte0[0~7] were extracted for both the package and PCB designs. An example of bit[0] is shown in figure 4. S-parameters among these four conditions did not change significantly within 10 GHz. The worst case had a 0.6 dB decreased in insertion loss when temperatures reached 165°C.
Fig. 4: Insertion loss and return loss of ddr5 bit[0].
Power delivery network and AC noise measurements were compared with and without thermal impact in the two scenarios. The entire PDN with Rdie and Cdie had a peak impedance at the same frequency at these four conditions. The variation of the PDN values comparing to the first one, 25°C original, were -3%, -2% and -7%, respectively, as shown in figure 5 (A).
The tolerance of AC noise among these four conditions were 0.3%, 6%, 16% and 14.5%, respectively, when each utilized a current model based on different process corners as shown in figure 5 (B).
Fig. 5 (A): PDN measurements.
Fig. 5 (B): AC noise.
As a baseline, the channel simulation of the eye diagram of DDR5-4000MT/s byte0, optimized the best driver mode and on-die termination (ODT), respectively, and the power of the input/output buffer information specification (IBIS) model was set for the package and PCB layouts. Even though the performance of byte0 among these four conditions had clear eye openings, the comparison was able to distinguish how the eyes were affected by thermal performance. Looking at eye diagram of bit [0] in each condition, the eye-jitter-peak-to-peak (P2P) were 8.4 ps, 9.6 ps, 16.1 ps and 16.9 ps, respectively, and jitter-V-crossing of eye-level-one were 67.9 mv, 86.1 mv, 159 mv and 168 mv, respectively. Furthermore, the fourth condition, 85°C with thermal, had the worst jitter in both the horizontal and vertical crossings. Figure 6 shows the four conditions.
Fig. 6: Eye diagram of ddr5 byte0 in four conditions.
With optimized package layout and PCB designs verified by electrical simulation as the baselines, all electrical performance with room temperature met initial requirement. However, this work indicates that electrical simulation items related to power rail should be considered carefully with thermal impact, including IR Drop, RLC values, AC noise, and eye diagrams with SSN, because the resistance increases when temperatures rise. For instance, if AC noise should be limited to less than ±5% to meet the specification at room temperature, 25°C, even if it is optimized to 0.3% it failed at temperatures higher than 85°C. Optimizing the layout, such as re-routing power nets or bypass capacitors, will be a main task when considering thermal impact.
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