Custom Chip Verification Issues Grow

No simple solutions to deal with market-specific requirements and advanced process node issues.


With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom.

As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including analog/mixed-signal (AMS) design, where interfaces and protocols used for each project are different.

“If the design is relatively simple, it’s not such a big deal,” said Zibi Zalewski, general manager of the hardware division at Aldec. “But when we approach SoC projects for ASICs, and recently FPGAs, it becomes important for current and future projects to keep with the standards, at least company-wise.”

This will simplify reuse of those projects in the future, but what is really important is that it won’t require major changes for the verification environment. It is an extreme effort to develop items like bus functional model simulation and SCE-MI transactors for emulation, which are expensive if purchased for each new project.

Custom design verification challenges are further exacerbated by specific reliability requirements for different market segments, such as automotive and mobile. That means the tools need to run fast enough to deal with huge amounts of data and variation, and they need to be able to analyze aging, self-heating, electromigration, and other physical effects. And as Anand Thiruvengadam, senior product marketing manager for AMS at Synopsys, pointed out, these capabilities need to span traditional SPICE and FastSPICE simulator technologies.

Analog plays a starring role in custom design, and all analog circuits have significant circuit verification needs. That starts with verifying basic functionality, but it also requires quite a bit of characterization to ensure that the design will operate as intended or meet its specifications across all environmental operational and process variation, said Mick Tegethoff, director of AMS product marketing at Mentor Graphics.

“Within analog design, you’re going to have different requirements for verification depending on the target application for that analog design,” Tegethoff said. “For instance, in the case of the ubiquitous ADC (analog-to-digital converter) block, depending on the performance specs, the verification requirements can become very stringent, and the verification becomes more than just, ‘Does this ADC take a sine wave and turn it into bits?’ If you have an ADC that’s part of a wireless transmitter receiver in a cell phone, it has to survive all kinds of interference, from noise or otherwise, so the amount of verification that a designer will have to apply to a circuit like that is much higher than for a garden variety ADC that goes into a price book somewhere.”

In automotive, analog circuits control all of the mechanical aspects of the automobile —seats, brakes, ignition — and each of those has a whole new set of requirements that are really related to the environment those designs are going in. These are typically implemented in technologies like BCD, which have high-voltage transistors at the end driving the motors. Here, there is huge concern about the heat those power transistors dissipate and how it effects other circuits on the same chip. Then there are liability concerns, ISO 26262 certification, and a wide variety of verification needs. Requirements vary greatly, depending on the type of application.

In other custom circuits, such as high-speed interfaces or any kind of SerDes, high-speed serial data has stringent verification requirements from bit error rate to jitter, and just making sure these devices work at various frequencies and data rates. “You also have to make sure the noise that comes from the devices themselves (device noise or thermal noise/flicker noise) needs to be included in the verification because it plays a big part on the jitter specs,” Tegethoff said.

RF adds its own unique problems. Any kind of on-chip RF CMOS has verification requirements that, in addition to the traditional circuit simulation, requires some analysis to be done in the frequency domain. Verification engineers generally look for such things as phase noise and noise power, then apply analyses like harmonic balance and periodic noise, which are all required for RF type circuits.

And then there is another layer of complexity to deal with—parasitics.

“In a very large geometry, low-performance application, the design can be simulated pre-layout, which is a pretty quick simulation,” said Tegethoff. “But all of these high-performance, low-geometry analog circuits need to be simulated pre-layout, and then again post-layout. That adds a huge number of elements to the simulation, so the simulation takes a long time.”

A final vector is PVT. “In the past, it was enough for an analog person to take their circuits and do the verification that digital engineers do for standard cells, which is basically the PVT,” he explained. “You run your process, voltage, temperature corners and you pick a number of corners. In these precision, high-performance analog circuits, they need to actually do more than that in the nanometer technologies. They need to do a lot of Monte Carlo so they can actually understand the variation of particular devices, not just across the whole process. But they have device mismatch that they need to see what happens if these two transistors get out of control. They also want to know what it will do to the actual measurement of interest, so they are running hundreds, thousands, tens of thousands of simulations. The higher the reliability of the application, the more simulations they need to run.”

The challenges don’t end there. For 2.5D designs, there are gaps in the verification tools, according to Deepak Sabharwal, general manager of eSilicon’s IP products and services. “You can run LVS on the chip-level part, but there is no tool to do extraction for LVS across the chip, interposer and HBM stack. You wind up with a lot of scripting and custom flows to get this done. The same problem exists for timing analysis. There are no RC models for the interposer, so you need to go back to basics and use a field solver to get models for this part. Inductance is a key factor for these materials, as well.”

Verification of high performance design at the chip level has other challenges, he said. “On HBM2 PHYs, electromigration and voltage-drop analysis are influenced by circuit activity. One must determine the right data traffic to represent a worst-case situation to be sure things will work correctly. These technologies are also based on complex JEDEC standards, so finding robust verification IP to validate that the IP correctly implements the standard is also important.”

When it comes down to it, there is some aspect of every design that is custom. The question is how much?

“It could be a custom block for an important function, it could be the way in which IP is configured and connected,” observed Adnan Hamid, CEO of Breker Verification Systems. “It could be in a systems performance of power characteristics. Or it could be in the software that is put on top of a standard architecture. While there is some expectation that third-party IP works on its own, it has to be integrated and you have to verify that the system-level functionality is actually present and performs according to the specification.”

While challenging to verify, custom designs give semiconductor designers and systems companies a differentiating edge. But success out of the gate requires a comprehensive understanding of the target application, along with a thorough verification of the entire system. That means more Monte Carlo runs than ever before, more time and effort, and a thorough understanding of what’s involved in making sure these chips will work as expected.