DC Bus Switching Performance as Determined by Commutation Loop Parasitics and Switching Dynamics

Dig into the details of how an inverter stack-up with the new bussing design showed ultra-low overshoot and clean switching three-phase.


In this article a 250 kW all-SiC inverter evaluation kit designed around low-inductance, high-speed power modules is used to demonstrate the DC bus switching performance resulting from the interaction among commutation loop parasitics and the switching dynamics. The interplay among the DC bus structure parasitics and near-RF switching dynamics can be quantified in both the time and frequency domains. The gate driver external turn-on and turn-off gate resistor selections in the gate-source signal path directly impact the system response – and whether it is critically damped or underdamped. The parasitic ESR and ESL of the DC bus film capacitors, laminated bussing, high-frequency (HF) ceramic decoupling capacitors, and power module-DC bussing interconnects contribute to bus switching degradation due to fast SiC MOSFET switching dynamics. The key takeaway is to optimize the DC bus structure rather than trying to compensate for a poor design.

Read more here.

By Ty McNutt, Kraig Olejniczak, Daniel Martin and Guy Moxey; Wolfspeed, a Cree Company, USA

Leave a Reply

(Note: This name will be displayed publicly)