Minimize the cost of testing ARM processor-based designs and other multicore SoCs.
A significant design trend in recent years has been the widespread use of ARM multicore processors in systems-on-chip (SoCs). Designers’ ability to easily and cost-effectively employ multiple, high-performance embedded processors to meet the computational demands of the end application has helped fuel the explosive growth in mobile computing, networking infrastructure, and digital infotainment systems.
Teams developing these ARM processor-based designs and other multicore SoCs have had to implement design-for-test (DFT) to achieve their test quality goals. But a key challenge has emerged: as the number of processor cores increases, it becomes more difficult to meet these goals cost-effectively, given the limited number of pins available for testing.
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