Drowning In Choices

The number of options available these days is huge, and there’s no easy way to sort through them—but they all have to be considered from the outset.

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There are at least half a dozen possible options for 28nm process technologies. There will be even more for the finFET generation. And that’s just the beginning of how complicated things will become over the next few years.

There are multiple ways to test, seemingly infinite numbers of IP offerings—even from the same IP providers—and even more packaging options to put them together. This is no longer just about build versus buy. It’s even confusing about what to buy and how to integrate all the pieces together.

This is compounded by the fact that to speed up chip development, with an eye toward keeping down costs, staying within power budgets, and offering enough performance to remain competitive, all of these factors have to be considered up front. That’s a lot of decisions, and often one is dependent on another. Logistically, this is overwhelming, and so far there is no simple way to sort through it all.

The challenge stems from the foundations of how chips are created in the first place. Architects choose materials and approaches based on what’s best for them, which in the days of Moore’s Law scaling was rather straightforward. Then it was handed off to other groups, which chose the best packaging and test options.

However, at 28nm, the number of decisions that need to be made up front increases significantly. For example, what goes into hardware versus software is a complex calculation based on best guesses. There is no simple formula for this other than finding people with experience in this area. How a chip will be tested likewise isn’t so simple anymore. At 28nm and beyond, and particularly with finFETs and 2.5D/3D architectures, the entire SoC has to be designed for test because there are so many possible interactions. Does that get accomplished through internal BiST or through external connections, and what exactly should be tested?

There are tradeoffs on processes that can affect everything from the number of metal layers to the overall power/performance equation. Do companies stick with bulk CMOS, swapping in high-k/metal gate technology, move to FD-SOI, or push to some combination of both at advanced nodes with finFETs? And on the design side, there are even more configuration possibilities with 2.5D and 3D-ICs, including some new variants of 3D-IC that don’t use through-silicon vias.

The problem is that each of these tradeoffs has a benefit and a cost, but some of those costs aren’t so easy to calculate because they depend on other choices. While there are cost tools for managing bills of material, there are no tools for managing those costs coupled with trading off one IP block for another or one testing strategy versus another and the market opportunities that greater performance can bring. Most of that is done by experience, and experience doesn’t always provide a comprehensive picture because there are simply too many variables these days for the human mind to grasp, no matter how much experience an engineer may have.

We are entering a new era of complexity, and it’s one that needs to be fully understood from an ROI perspective with plenty of flexibility built in for other options. So far nothing fills this void because it isn’t simple price swapping of components. But for the semiconductor industry to move forward, this bridge will need to be constructed.