Advanced Packaging Fundamentals for Semiconductor Engineers

Advanced packaging is inevitable. Large systems companies and processing vendors already are working with various types of highly engineered packaging. The rest of the semiconductor industry will follow at some point, whether they’re designing their own packages, developing the tools, processes, materials, and methodologies to create them, or developing components that will be used inside of them.

After 60 years, Moore’s Law as applied to a single die has run out of steam. Wires, SRAM, and analog don’t shrink at the same rate as digital logic, and trying to force everything into a reticle-sized, planar SoC is counterproductive. Performance and power benefits are limited, and the cost of pushing everything into 2nm or angstrom processes is prohibitive.

But as companies that have made the leap to some type of multi-die package have discovered, there are so many possible options and optimizations available that it’s difficult to keep track of them all. There are fan-outs, fan-ins, 2.5D, 3D-ICs, logic on memory, memory on logic, logic on logic. The list goes on. Each comes with its own set of benefits, tradeoffs, and challenges, and new ones are being added all the time.

Semiconductor Engineering has compiled a comprehensive list of the types of packages, what’s included in them, and various processes used for assembling them. Included in this report are discussions about how to design these packages, how to build and test them, how they behave in the real world, and where problems can crop up.

This report is written primarily for engineers working in various aspects of the semiconductor industry. It contains a lot of material, some highly technical, gathered from hundreds of interviews with experts, conference presentations, and technical papers, including new directions and challenges.

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