How to achieve a DRC-clean, manufacturing-ready design at advanced nodes.
Manufacturing chips at 3nm and below is a challenge, but it’s only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wilson, product management director for Calibre Design Solutions at Siemens EDA, talks about what’s needed to get a design ready for manufacturing, what’s involved in a DRC-clean design, and how that can help minimize IR drop and account for electromigration.
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