Combining geometric and topological data for better reliability verification.
As a designer or verification engineer, you’re fighting the effects of electrostatic discharge (ESD) in your integrated circuit (IC) designs all the time. ESD is one of those frustrating issues that can challenge even the most experienced designers. Once an IC is in the market, unexpected electrical shorts will cause immediate failure or dielectric breakdown will result in gradual circuit degradation. Products that die unexpectedly or fail to deliver the promised performance do not impress customers.
The time to protect your IC against ESD starts long before manufacturing, of course. IC designers must make sure that ESD protection devices are properly implemented in the IC layout, and that ESD discharge paths are efficient and robust (figure 1). This verification is usually done in a bottom-up process. First, designers ensure that individual library cells comply with ESD requirement for metal robustness and resistance limits. Next, they verify the compliance of an I/O bank (cells within the same power supply domain) against those same requirements. Finally, they confirm every pin combination on the chip has a designated ESD current path, including pairs of pins belonging to different power domains [1].
Fig. 1: Device-based vs. cell-based ESD network.
However, one thing that makes this verification challenging is that reliability requirements like ESD protection typically can only be described by a topological view that combines both circuit description and physical devices [2]. This ability to combine geometric and topological data, including the identification of possible areas of electrical failure, geometrical constraints of device dimensions, the number of device fingers, distance from supply pads, and different circuitry requirements for multiple power domains [3], is not a common capability in most electronic design automation (EDA) tools.
In addition, point-to-point (P2P) parasitic resistance and current density (CD) checks are an integral part of ESD verification. While these checks are often supported by foundries, they may not cover all ESD devices, and detecting and verifying an ESD structure is not always trivial for designers without specialized ESD knowledge. So, how do we get adequate ESD protection verification?
One way to make these checks easier to use is to adopt an approach that detects these devices using the cell name instead of a complex topology definition. In a typical device-based verification flow, it is nearly impossible to preserve cells, as device extraction has the highest priority. Even if the cell exists in the layout, the verification tool probably can’t recognize it. In addition, the hierarchy is not fully respected.
However, ESD cells are typically well identified in a design, because the cell name contains very specific keywords like “ESD” or “CLAMP.” Only the cell name and port names are needed to define a new ESD cell that can be used with all ESD checks. The only thing we really need is a tool with the ability to run cell-based checks.
But, as we already mentioned, ESD protection verification also requires a topological view that combines both circuit description and physical devices. Fortunately, there are some EDA tools, like the Calibre PERC reliability platform, that provide cell-based checking in combination with logic-driven layout (LDL) technology that enables the tool to combine geometric and topological information in a single check. The LDL functionality is essential to many reliability checks that are driven by interdependent constraints (e.g., current value is dependent on interconnect spacing) [3].
To streamline the use of reliability verification, the Calibre PERC reliability platform provides a set of well-written, pre-coded checks, including cell-based checks, contained in an easy-to-use flow that enables designers to run these checks without the need for custom check coding at runtime. The packaged checks framework makes it easy for designers to quickly and accurately identify and evaluate ESD structures using a Calibre PERC cell-based ESD check, even if they do not have much experience with ESD checking. Straightforward selection and configuration of these pre-coded checks maximizes ease-of-use and minimizes runtime setup.
The Calibre PERC cell-based verification flow uses packaged checks for both P2P and CD checking. When LDL cell-based checks are executed, device extraction is disabled, and all trivial pins (those pins not connected to devices) and empty sub-circuits are preserved in the extracted layout netlist for topological analysis. These conditions facilitate checking of connectivity to any desired cell port (where the cell acts as a hierarchical cell). Because device extraction is not required when running LDL cell-based checks, an LVS-clean layout with devices present is not a prerequisite for running LDL checks on cell placements. Also, because the device modules are skipped during circuit extraction, cell-based checks generally run very quickly.
For example, checking that the primary protection is properly connected is very important, but it typically requires P2P resistance and CD checks. With the cell based flow, designers can use the cell name (ESDCell) and its ports to run a resistance check from any pad to all ports of the ESDCell. In Figure 2, the primary protection is the grounded gate NMOS. The two ground ports (gnd_B and gnd_S) enable designers to make two different measurement on the same net at two different points on the cell.
Fig. 2: Grounded gate NMOS protection device and cell based circuit.
The ESD cell-based P2P and CD checks also enable designers with any level of familiarity in Calibre PERC usage to build a variety of P2P resistance and CD checks for ESD validation. Any cell can be used and defined as an ESD device, which allows designers to work with a bottom-up approach. Once a macro block is fully validated for ESD, this block can be defined as a new ESD cell to check the top-level connectivity.
In an ESD protection circuit, clamps are the devices used to provide the discharge path for an ESD event that happens between any pad and port. Clamps include not only power clamps, but also all the other ESD protection that will form the ESD network. Their ability to manage the excess current in an ESD event can be affected by parasitic resistance and current density. The Calibre PERC cell-based P2P/CD packaged check can run complex P2P and CD full-path checks, using very simple and flexible rules that cover three check types: pin to clamp, clamp to clamp and pin to pin [5]. Table 1 displays the details of each check, while Figure 3 provides examples.
Table 1: P2P/CD Packaged Checks
Pin-to-clamp
The pin-to-clamp check finds all possible combinations between all pins of the specified type (power/ground/IO) and all specified clamp types. The check then calculates the parasitic resistance on each combination.
Clamp-to-clamp
The clamp to clamp check finds all possible combinations from all clamps of a specified type to all clamps of a specified type. The check then calculates parasitic resistance for each combination.
Pin-to-pin
The pin-to-pin check finds all possible combinations between all specified “From” pins and all specified “To” pins. The check then calculates a full path resistance calculation for each combination.
Fig. 3: The cell-based P2P/CD packaged checks cover three check types: pin to clamp, clamp to clamp and pin to pin.
The following constraint configuration demonstrates the setup of a clamp-to-clamp P2P parasitic resistance check. The starting point is the grounded gate N-type MOSFET (ggnmos), and the ending point is the closest power clamp. The maximum parasitic resistance allowed by the check between these two points is 1 Ohm.
<Constraint Category="ESD_P2P_Checks" Name="ESD.CDM.SEC.1">
<Parameters>
<Parameter Name="checkType">clamp2clamp<Parameter>
<Parameter Name="fromTypeList">ggnmos<Parameter>
<Parameter Name="toTypeList">clamp<Parameter>
<Parameter Name="max_res">1<Parameter>
<Parameter Name="comment">Resistance of the bus line from ggnmos to the closest PowerClamp less than 1 Ohm<Parameter>
</Parameters>
</Constraint>
The check reports results for all ggnmos ESD protection that have the metal resistance to their closest power clamp higher than 1 Ohm.
Using this syntax with different parameters, designers can create as many checks as needed and run all of them in a single run.
Results debugging
Results of P2P and CD checks are displayed in the Calibre RVE results viewing environment for viewing and debugging (figure 4).
Accurate and repeatable reliability verification is a critical capability, both for advanced node designs and the increasingly complex products being produced at established nodes. However, many reliability checks require a combination of geometric and topological information not readily available in standard verification tools. And, even with the availability of innovative tools like the Calibre PERC reliability platform, creating reliability checks for conditions like ESD protection is time-consuming, and requires expertise in both ESD verification and Calibre PERC coding. The Calibre PERC ESD cell based P2P/CD packaged checks provide a new and innovative way to quickly and accurately create rule checks that cover a variety of P2P resistance and current density checks for ESD validation, with only minimal experience using the Calibre PERC tool. By using the Calibre PERC packaged P2P/CD checks, designers can achieve faster, more accurate reliability verification while reducing time to market.
References
 |
 |
 |
 |
 |
 |
 |
 |
 |  |
Leave a Reply