Evaluating Speedcore IP For Your ASIC

By exploiting Achronix Speedcore embedded FPGA (eFPGA) IP — IP proven in multiple ASIC designs for wireless, datacenter and high-performance computing (HPC) applications — designers of SoCs can now add logic programmability to their solution, resulting in a single ASIC that can adapt to many applications. While many system architects may already have strong ideas on how an eFPGA core could add value to their ASIC/SoC design even before having formulated a specific application, it may not be clear how to start an evaluation. Often the question foremost on a potential customer’s mind is “How can I assess Speedcore IP’s ability to solve my problem?”

Achronix refers to this pre-engagement stage as phase zero — an evaluation period where customers formulate application ideas and test them using tools and models. This paper presents a walk-through of phase zero, providing guidelines to customers who want to explore and refine ideas for employing a Speedcore eFPGA in their SoC.

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