Experts At The Table: Changes In The Ecosystem

Second of three parts: Emphasis on integration and flexibility; where companies differentiate; tighter but more expensive partnerships; lithography changes; three vectors for chip design.

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By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation.

SMD: How are chipmakers working with the rest of the ecosystem today? Is everything in sync?
Quan: If you look at the development cycle, the first part is the definition phase. This is where we work with customers to do low-level device optimization and PPA—how much power it uses. Once you get through that, in order to do that, you have to look at what’s required. And with the EDA companies, we address the solutions, the road map for these solutions, and when these test chips will land. It’s much more coordinated.
Lim: All of them care about differentiating their own SoC. As a result, time to market is not enough anymore. If you’re designing a cell phone chip, your competitors are doing the same thing. How do you do it better than them? That’s why these companies want to partner with IP providers earlier. They want to do something else that’s different. You have to be able to design your IP in a way that’s configurable and customizable. For Cadence, that’s one of our guiding principles. That will be even more important at new process nodes because it allows customers to do another spin.
Kranen: We use a different term. We try to make our IP so it can be integrated in any environment. It’s always standard, guaranteed functionality, but you have to be able to integrate it. Can you customize it? Well, how much can you customize a USB on the outside? There may be a few things you can do. But the flip side is that while there is a need for differentiation, a lot of people don’t differentiate with the IP they buy. They want it to be reliable and on time with known functionality. They want to fill in the rest of the white space on their chip so they can focus in on the differentiation. The thing they’re going to differentiate is their own IP.
Buehler-Garcia: We can’t afford to do this with everyone. Our entire industry is $1 billion in R&D. We need to figure out how to get more value out of that. And if you look at who’s going to the advanced nodes and who’s buying DFM tools, it’s a very quick steep curve down. We can’t afford to put the resources that we put in the large foundries like TSMC into everyone. When the ecosystem started, the foundries gave us a spec, we looked at how to implement it with our tool or IP. Now we’ve got hardware in place, we have simulation, and we’re coming back to the foundries and saying, ‘We’ve looked at what you are doing. What about changing this?’ This is optimization round two. And then we start talking with customers and said, ‘We can get this done faster for your analog designers.’ We probably wouldn’t have had that discussion in the past.
Quan: Yes, it’s not a one-on-one anymore.
Buehler-Garcia: And forget the idea of control. We’re all chatting with everyone else. The companies that go into the ecosystem have to get comfortable with not trying to control everything. We compete on a whole bunch of things.

SMD: Lithography is a huge issue. Where are we?
Buehler-Garcia: EUV works, but does it work for the volume you need to do in a foundry? We have to support everything. Still, if the industry is working on three different options, then we need to be working on three different options.
Quan: We’ve been working through 20nm and 16nm. At 20nm we went through double patterning and we know how to solve it. All of the tools can handle it. At 16nm we have a new front-end. All of the investment is going into double patterning.

SMD: How about the one after 20nm?
Quan: That’s 10nm.
Kranen: At 16nm and 14nm we understand the back end of line. But the next big shakeup is triple or quadruple patterning, or self-aligned double patterning.
Quan: If EUV is not there, we will continue to do patterning. It will probably be quadruple patterning on a couple layers.
Buehler-Garcia: One doesn’t exclude the other. We could have some layers on EUV, some on triple patterning, and some on double patterning.

SMD: So the collaboration has to tighten further, the investment is higher, and the number of partners is extremely limited?
Buehler-Garcia: That’s true at the beginning, but the key here is the tail. There’s a very long tail. We’ve been talking about 10nm and 14nm, but the number one node today is 28nm, and the majority of tapeouts were over 65nm. There is a boatload of 0.35 and 0.25 micron. And things we learned with PERC (programmable electrical rule checker) we’re seeing adopted all the way back to 0.35 microns.
Kranen: There actually are multiple sweet spots. We always talk about the leading edge, but there’s the BCD (bipolar CMOS DMOS) process used by automotive and for high voltage, and it’s a mix of digital, analog and bipolar. That is seeing a lot of life.
Lim: But in terms of more advanced nodes, is there more investment? Yes. But everyone is innovating in the ecosystem. When you start coming to, ‘How do we solve the problem together to make it easier,’ we adapt to these changes. It’s going to be a process of adaptation. The tools will adapt. The IP will adapt. And eventually it’s all going to be optimized.

SMD: If the tail is getting longer, are fewer people moving as quickly on the leading edge?
Kranen: There are more guys at the front end. Is there an economic benefit for the consumer? It appears so.
Quan: The lead node is 28nm. We have all the capacity now. That will likely stay around for some time. Even 65nm and 40nm are doing well. Because of the move from 20 to 14nm, though, using the same process, it’s not a two-year cycle anymore. It’s one year. Customers who haven’t moved to 20 or 16, they now have a choice. It used to be two years out, you went to the next node. Now because it’s only one year apart, the guys at 40 or 28 may think about how to optimize their product.
Lim: When you think about the Internet of Things and all of these mobile devices, they’re all driving big data, and that’s driving performance. We don’t have enough servers. That’s a reason they have to go down to the next node because the finFETs offer a power advantage.
Kranen: It’s not just power. There’s also a price component. There is a lot of pressure. That will force everyone into new processes.
Buehler-Garcia: And this involves just one option, which is linear scaling. The other option is 2.5D and 3D.

SMD: Where are we with that?
Quan: The FPGA guys were the first to announce that. They split up their array into more pieces with a homogeneous approach. We also are starting to see heterogeneous versions with SerDes. That’s on the way, but it still depends on price and performance. The whole price point has to be justified for other markets.
Lim: That will require even more partnerships and collaboration. There is a lot of work just in getting Wide I/O to work. And moving forward to 2.5D and 3D will require even more collaboration.
Buehler-Garcia: But it does give you more options.

SMD: This is a subsystem play, right?
Quan: There are three very clear vectors in the market. One is pushing Moore’s Law. The other is mainstream technology. At 0.18 we have derivatives around that for high voltage, high BCD and CMOS sensors. We continue to invest there to make sure the analog and mixed signal guys have ways to address their piece. The third piece is stacked die. Not everything can go down to 16nm and 10nm. We can hardly do analog at 28nm. A lot of things will stop where they are, or at the best node possible, and then be assembled into a stacked die.
Lim: It’s all about cost.
Buehler-Garcia: We’ve been on stacked die forever. What’s changed is the interposer and how we make it go forward for the new stuff. It opens up a whole different set of issues. We are all becoming system integrators. But who owns that? And who gets the margin on that? The other piece is the memory. We need full GDS II. We dealt with this when the foundries started up. No one wanted to give up GDS II. It took some time to get people through that.