Experts At The Table: Improving Yield

Second of three parts: Improving information exchange; the impact of software; dark silicon; through-silicon vias and electrical effects; stacking die in 2.5D and 3D configurations; testing issues; DFM challenges; the limitations of interposers.

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By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: How good is the information exchange across the supply chain these days?
Capodieci: We need to push a lot of design information onto the manufacturing floor. This is a huge area. The EDA industry really needs to wake up and create a new set of flows. This is one of the most advanced industries in the world. We fabricate sophisticated devices without actually knowing what we’re fabricating. We ask for less-than-optimal information about where the critical issues are. New flows and new interfaces can be added to the manufacturing floor, respecting the IP and the proprietary nature of the design. But the information can be passed on to the manufacturing floor so it can be monitored and acted upon.

SMD: We’re not just creating hardware anymore. How does software affect yield, and is it even considered part of yield?
Michaels: If you look at the fabless sector, they’re hiring multiple software engineers per design engineer. It’s where a great deal of effort is going. But for our purposes, once you get past test and packaging and yield we tend to view it as the fabless problem. It’s not our market.
Mason: At TI we’re investing enormous resources in software and compilers that our customers use. It’s something we have to deliver to the ecosystem to use our products. We’re not using software to fix a yield problem. We’re typically not coupling the software with the fab yield problem right now. It’s more of a design enablement activity.

SMD: Will that change?
Mason: There’s more and more integration across the entire design space, and that includes software. Software is a critical part of what we do on the product side.
Capodieci: In the foundry space, we are still very active in doing esoteric R&D with universities. This is a little futuristic, but we have seen interesting research out of UCSD (University of California San Diego) on dark silicon, which is the silicon that does not get activated. We make it fully functional, but it is hardly used because of power issues. So there are software techniques and architectural techniques that go into making the best use and creating opportunistic cores. This is beyond our traditional field, but in the future we need to keep an eye on how the architectures will evolve with a focus on what needs to yield with a certain variability level and what needs to yield with a different variability level. This is an approach I call managed variability. Not all of the physical components react equally to the process. We need to be able to distribute this, but we need to know which components we’re building. This will be beyond 20nm.
Ramaswami: Most of our investments in software have been in three areas. One, of course, is process design. When you have very deep vias, you have diffusion of materials from the very top to the very bottom. A lot of the modeling has to be done in terms of concentration of gradients as well as mechanical agitation. The second area is around chamber control. When you have a multichip system, how do you measure the parameters? The feedback to the system becomes critical. An example is CMP, where you look to measure in real time the thickness of the materials and you control the polish rate. These get very critical with 10nm or 15nm films at the gate level. The third area is for inspection, where inspection and analysis are becoming a big deal at the wafer and at the mask level.

SMD: What happens with stacking of die and we have to drill holes in the silicon? Where are we now and where will be in a couple years?
Ramaswami: Most of these vias are made in the via-middle process, which is basically a blind via and done right after contact. You have the contact formation to do the blind via, you etch it, line it, and it’s all done. Or you assume it’s done, because you have no way of really knowing. Of course we can do some X-ray analysis at the full wafer level, but we only get ghost images of gray and white. It’s like looking at an ultrasound. You have to be a trained radiologist to figure out what it is. You’re sending the wafer on and putting faith in the rest of the logic line, which may be 10 or 20 layers, each one going through a heat cycle. You’re just hoping the via is in good shape at the very end, and you really don’t know until you do backside testing. In terms of mechanical yield and cross sections, we believe today that filling the via is not an issue as far as structural analysis is concerned. How well it is done electrically, with heat cycles, we just don’t know because data is limited. And often a different side of the fab—the packaging side—finds the data. That feedback loop takes a long time.
Capodieci: In terms of 3D, we’re a little bit behind—particularly with extraction. The problem becomes bigger, of course. But the process side is ahead of the curve. Still, it’s something that needs to be brought to fruition if we are going to bring 3D architectures to market.
Michaels: From the foundry standpoint you can’t completely test at the single-chip or wafer level. That will require the foundries to use more equipment data, more characterization, to find a probability to finding out how close they are to being in the center of the process. You may not be able to test exactly but you can clearly determine when should you scrap, etc. These new techniques of leveraging more data out of the fab than traditional metrology will become more important.
Smayling: In stacking, one of the opportunities for yield improvement stems from the fact that fab inspection traditionally has been on a surface. We’re going to have to think about how to inspect these stacked structures. It’s something we don’t have technology for today, but it’s going to be needed to drive these activities. For EDA, whether they’re stacked or not they’re going to be designed piece by piece. One of the biggest problems for EDA is that each of the pieces is done potentially at a different technology node. Now you’ve got a PDK that works with one version of verification software, a different PDK that works with a different version of verification software. And so when you stack these things together there’s no consistent environment for even doing verification. There is a big opportunity for verification to take on these kinds of issues.
Mason: There are lots of challenges with 3D. TI is right in the middle of those kinds of technologies because that’s the way the industry is heading. One issue that’s important in all of this is DFM. There are all kinds of mechanical stresses in this process, and these mechanical stresses have electrical implications. Where these TSVs are on the wafer relative to transistors and whether those are timing-critical circuits that are impacted by mechanical stresses has to be considered. There is research in this area now. We haven’t worried about these DFM issues in the past, but we will have to.

SMD: What kinds of mechanical stresses?
Mason: Where you physically change the silicon and that has an electrical effect. If you take a chip and macroscopically bend it, that affects the speed of transistors because of the electrical impact of that strain. When you’re doing that locally, you can change the timing of that circuit and break the circuit. That can happen because you’re putting a through-silicon via there that you didn’t simulate.

SMD: Stacking in 2.5D seems much more straightforward compared to full 3D stacking. Which one will come out first and why?
Ramaswami: I think 2.5D is much simpler. But we see the end market today driven by mobile devices, which requires a DRAM stack on top of a logic chip. That clearly does not lend itself to 2.5D or interposer technology. So we need to get that working, no matter what. The questions we’re getting now on 2.5D is how to make the interposer more active rather than just having a piece of silicon with lines through it. Putting more capacitors and inductors on them is an area we’re beginning to pursue with a couple of universities.