Experts At The Table: Improving Yield

Last of three parts: Stress effects from TSVs; testing stacked die; simplifying design rules and shifting from what’s not allowed to what is; the effect of 450nm and re-use on total cost.


By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: What’s the big challenge with 3D stacking from a DFM perspective?
Ramaswami: People want to put a couple of vias in the place of one because they don’t know if the first one is filled or not. What happens is you put a lot of strain on the transistors adjacent to them—5 microns, 10 microns or 15 microns away. In response to that, people want to shrink the via dimensions, but that’s not practical to fill. This is where design, manufacturing and design for manufacturing all come together. Right now the industry has a sweet spot around a 5 to 6 micron CD (critical dimension). Let’s get that working first before we move onto other dimensions.

SMD: How about testing of these stacked die?
Mason: We’re feeding design for manufacturability risk areas into the ATPG (automatic test pattern generation) flow. We’re informed by our analysis of the chip of what likely problem areas might be—stress, TSVs, lithographic hot spots, or strain-induced problems—and we feed those locations into the test pattern flow and they set up test vectors that are diagnostic against those problems. One of the solutions I see is heavier use of ATPG. If you have informed manufacturing people who can anticipate where the problems might be—and I think we can—then you can develop test methodologies targeted for those problems. That’s part of the answer.
Smayling: A big problem for test will be that these 3D chips are different functions. If you’re used to working with logic testers and now you’ve got DRAMs or NAND flash or mixed signal, do you call up three different test guys? It’s going to be a real nightmare to integrate test and to make it cost-effective.
Michaels: I agree that test will be a great challenge. The other fundamental issue is that failures at the stacked die level are extremely expensive. How you minimize failure and catch it upstream through probability of good die, through system disaggregation and choosing the right technology for the right chip will fundamentally have a big impact.

SMD: The cost escalates not just because of the design, but also because of a larger bill of materials, right?
Michaels: Absolutely. You’re throwing out multiple chips and the packaging for something that is likely a single chip or integration failure. You have to catch those early on in the process or it’s going to be extremely uneconomical.

SMD: Will we see more restrictive design rules as we move down Moore’s Law and into 3D?
Capodieci: The complex set of design rules that have been burdening the design manual since 65nm will be radically simplified. That does not mean designs will become simpler, though. They will become more regular. The problem with the complex set of design rules is they need to deal with a very large number of exceptions. When we have extremely regular functions, we’ll also be able to simplify the design rules. There’s been bad synergy between design rules and design when designers became more creative. We are now at a point where everything will become simpler, but new criteria will have to be introduced at the physical design level. What we’re looking at here are special constructs that violate the design rules but which achieve manufacturability.

SMD: But if we put die A on die B, we may be creating a bad die from two known good die, right?
Capodieci: That’s correct. We need to start thinking in 3D. The density is now an issue. What kind of thermal densities will we create? There will be rules for 3D, but they will be subsumed by the fact that we will start thinking about those rules in 2D, as well.
Michaels: Those issues exist today with differences in density. The super-linear growth in design rules was driven in part by trying to define what is not allowed. If you look at any hyperspace of design rules, it’s looking like Swiss cheese. You have to make the transition or flip to defining what is allowed. What patterns are allowed vs. what isn’t allowed? That’s a big change for designers, and it’s a way for foundries to help them make the best choices. At the leading edge you’re starting to see a closer partnership between the fabless companies and the foundries.

SMD: As we look at 3D and advanced 2D, there also is more rationalization to match functionality with what’s needed. Does it make sense to move analog IP to 14nm, for example. How are these changes affecting design?
Mason: If the 20nm node is going to cost you so many dollars per square millimeter of silicon, and 130nm or 180nm analog silicon running on depreciated capital equipment is going to cost you 10% or 1% of that, with proven yield, and you have a cost-effective way to integrate that with a 3D solution, it’s a very simple business problem. That assumes you have a way to do it and your architecture allows you that much decoupling of your analog systems. There are issues there. Sometimes a little bit of analog needs to be proximate to some other circuit. But we will take full advantage of the fact that we have this enormous analog infrastructure and digital infrastructure in the same company.
Ramaswami: Any new application is an opportunity, for sure. Having said that, this is the first time I’ve seen in a long time where a customer’s customer, a customer and Applied are all working together to see what can be done and what should not be done from a technical and a cost point of view.
Smayling: A regular design allows a surprising amount of integration of different functions. The tremendous improvement in variability of critical dimensions is something the analog engineers are interested in getting a piece of. That regularity can extend back to older technology nodes. The whole debate about regular design vs. 3D complex design is driven by people trying to sell supercomputers to do very complex point solutions to increasingly complex problems.
Mason: One of the reasons you do regular designs is you can certify them. They’re known to be good, and you can make aggressive decisions because you know what’s going to happen. But if GlobalFoundries has one set of regular designs, TSMC has another, UMC has another and SMIC has another one, how do you standardize all of this? It’s one thing to talk about regular designs in the IDM space, but when you’re talking about commoditized silicon manufacturing, I’m not sure how to do that.
Capodieci: The overall family of forbidden patterns is more a function of the technology and the technology node. We’re all dealing with the same wavelength and materials. The secret sauce lies not in a special solution. It is reasonable to imagine the patterns will overlap about 95%. The difference will be when we go to the esoteric stuff—more than Moore. That will have radically different shapes and the designs will be radically different. But as long as we keep pushing optical lithography, immersion and on to EUV, we’re going to see the same patterns.
Michaels: At the end of the day there are going to be differences driven by design rule choices, integration choices and material choices. You’re still going to want to maintain your designs at the physical layer. You’ll want to maintain your design requirements—your track height, your pin access, etc.—but fundamentally you’re going to have to do a port anyway. And porting may be easier in a pattern-based world than a design-based world.

SMD: As we push time to market in design, does yield get affected?
Michaels: The challenge of accelerating design is keeping the costs in line. If you look at complex SoCs, the amount of unique IP required on every chip is going up. The desire to re-use hard IP is much greater. The challenge is, what that IP is placed next to can have a strong impact on the parametric or functional unit. How you get to the point where you can re-use IP more effectively comes back to driving from the elimination of the unknown stuff.

SMD: What happens at 450mm? Does yield go up or down?
Michaels: The cost of a good die will go down.
Mason: Yes, and that’s the only thing that matters—cost.

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