Experts At The Table: Issues In Lithography

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation.

SMD: What are the big challenges in lithography?
Enami: Everybody is looking at EUV lithography. One of the bottlenecks for EUV lithography is throughput, which is caused by a lack of power in the source. Actually, we have not installed an EUV source to a customer yet. But existing EUV sources working in the field are still around the 10-watt level. The 10-watt level means the EUV throughput is around 10 wafers an hour. This is a big problem. Of course, the customer requires more than 250 watts of power. So, the big challenge is how can we provide high power and reliable EUV sources for customers.
Fujimura: Continuing to extend Moore’s Law will be a challenge. There are various different ways to approach that, including EUV, ArF extensions, nanoimprint and DSA. Direct-write e-beam is also one of the options. My personal feeling is to make sure ArF continues to be extended. If EUV works, or some other alternative works for a specific application, that’s great. But we need to secure something. And the best way to secure the next node is to extend what you already have because of the infrastructure issues. At D2S, I am focusing on ArF issues, while at the same time looking at direct-write and EUV. In ArF, one of the challenges and opportunities is to look at masks. At one time, it was so easy. You didn’t have to worry about mask accuracy, but that’s really no longer true. When you are using ArF, the dimensions on the mask are getting smaller and the shapes are getting complex. That creates a huge business opportunity for those of us in the EDA field.
Rey: From our perspective, we have never seen a node that is so close in production without having a clear of definition of what technology is going to be used for patterning. Right now, we are helping people bring in production for 20nm. Everything is pretty much defined there. But when we’re looking at 14nm, it’s seems like there are many options open. Our customers are investigating more than one technique. And that forces us to keep developing and doing research in more than one technique. Everyone seems to agree that’s it possible to move to the next node by multi-patterning or to go from double patterning to triple patterning. But then there is a big question associated with cost. Who’s going to be able to afford that? Then, when looking at the alternative techniques like EUV, direct-write or even with the early attempts with directed self-assembly, all of them need to have a little more maturity than what’s has been proven so far to bring them to full-level production. So, the biggest challenge I see is really the lack of definition on several different techniques. Each of them in the lab can deliver the level of resolution that is required, but each also has its own complexities.

SMD: To ensure that 450mm and EUV are on time, Intel, TSMC and Samsung recently invested in ASML. Are we seeing a new business model evolving in the equipment industry, where IC makers invest in fab tool vendors?
Enami: They are investing to ensure that they can obtain 450mm and EUV at the same time and in the most cost-effective way. Even ASML’s resources are limited. It’s very difficult to develop both at the same time.
Fujimura: It is getting to the point where there are clearly a smaller number of profitable companies that can afford to help with the funding. Sources of funding used to come from governments. They still do to a certain extent. But we are seeing a change on how things now get funded. I think it’s great that Intel, TSMC, and perhaps Samsung, are helping and realizing their responsibilities. They are, in essence, contributing back to the community by investing to make sure there is a future for the entire industry, not just for themselves. It’s necessary.

SMD: Will EUV make it for the 14nm node? If not, what are the options?
Enami: If we look at the technology, triple patterning is an option. Multi-patterning is an option. If we look at cost only, then we believe the 14nm node will use EUV. But 125 wafers per hour is the break-even point for EUV, and that requires around 150 to 200 watts of power. The timeframe for that is 2016 or so. So, we still have another three or four years. In the last four years, EUV’s power has increased 10 times. Today, it is at 10 watts. If we can provide a linear increase in power, it can reach 100 to 150 Watts. That means the customer has hope for EUV.
Rey: Double patterning will have a better chance for 14nm. But that is for those who can afford it. Some layers may require some triple patterning. That’s going to be pretty complex and expensive.
Fujimura: That also depends on the definition of 14nm. It depends on which companies you talk to. Each company has a different definition. Different applications have different measurements. I think the most meaningful measurement is time. 2016 is realistic for 14nm. I don’t think there is any question that it’s better if EUV can work as soon as possible. The degree to which things are being stretched to make ArF work is definitely pointing to more cost. There are other alternatives. People are trying direct-write e-beam. People are trying nanoimprint. People are trying DSA. But they all have issues. To a certain degree, they are all limited by funding. I wish that there was a sense of responsibility for the larger companies to fund those efforts. Don’t just stop with one thing. We need to create an infrastructure of alternatives and see what succeeds.

SMD: Will DSA succeed?
Fujimura: It might be too early to tell. Only certain sizes can be generated out of certain polymers. If we’re targeting 14nm, I’m not sure about DSA. What I understand is that DSA might not be quite ready for the next couple of years.
Rey: Mentor is part of the Semiconductor Research Corp. (SRC). Through SRC, we have been following DSA since the early research activities, especially with (University of Wisconsin) Professor Paul Nealey, who started with the first experiments. Through this sponsorship with SRC, we suggested to him to start looking into what were the key basic constructs to see what restrictions DSA would bring into the design community. Essentially, the DSA community has developed a credible path for some layers where it can be applied. However, there is quite a bit of extensive research needed for full-chip-level development. What happens from our side is that you need a model that can capture the key components of the process that you are using in a given manufacturing step. DSA is one of them. That model needs to capture the essential characteristics of a process, but it has to be applicable at the full-chip level. So, at the full-chip level, you have several billions of shapes or geometrical shapes. In DSA, we have not seen enough development that shows the models can be indeed applicable. So under certain conditions, the models seem to be simple. For general applications, the models seem to be very complex. We are not certain the models can be applied at the full-chip level. This is a central thing, which requires some attention. However, there are some industries like disk head manufacturing that have been using directed self-assembly polymers for a few years. And given that they have a very constrained type of shape, and not a very large design, they have been very successful using DSA.

SMD: What about the future maskless technologies?
Fujimura: E-beam is inherently very accurate. If we can do something like direct-write, where there are no mask costs and there are low volumes, I think this is important for the semiconductor industry. But it’s an investment issue more than anything else. If there was more funding it would be much more successful. It’s great that (TSMC Vice President) Burn Lin is promoting it, and in some ways, he’s funding it. There are other places that are doing it. The U.S. government is funding KLA-Tencor’s maskless lithography program. But I think the whole ecosystem is being stifled because of cost issues.

SMD: Where does maskless fit in IC production?
Fujimura: Complementary litho, which is being promoted by Yan Borodovsky from Intel, and David Lam, formerly of Lam Research, is a good way to introduce e-beam direct-write technology into the mass market. Basically, e-beam is great at drain holes, because it has a good depth of focus. What is it not necessarily good at is stitching long things together, because you have to shoot them separately. Being able to cut features is a great thing to ask e-beam to do.