Experts at the Table: Stacking the Deck

By Ann Steffora Mutschler
System-Level Design sat down to discuss challenges to 3D-IC adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of EDA2ASIC Consulting.

SLD: What is the best approach to pathfinding today?
Reiter: Four years ago I invited Riko Radojcic [from Qualcomm] to give a presentation at the GSA working group where we were focused on 3D. He presented pathfinding. To be honest, I was one of the many people who had no clue what he was talking about. So four years ago, Qualcomm already looked at this, which was really remarkable. In the meantime I have learned a little bit about pathfinding, and if you look at Qualcomm’s business in general, it’s consumer. It’s all about cost. So the earlier in the design process you’re getting a reasonable handle in regards to what it will cost you, the better your chances to make a cost-effective solution. It’s the same game with power—the earlier you can assess power dissipation of different alternatives, the lower the power of your final solution will be. Of course Qualcomm, a high volume supplier of cell phone chips—1 million units a day, probably more at this point—is very eager to get the right cost because as a consumer you don’t pay more than you have to. And let’s face it, everybody has a smartphone today because it’s cost-effective. If we would have to pay five times as much, maybe some of us would have a smartphone but not everybody, and that’s what keeps our lives getting more interesting and more useful. To get pathfinding, cost clearly is the primary objective. The challenge, of course, is pathfinding today does not have enough modeling information, enough library information, or enough building block information to really give you good results.
Bansal: There are some real challenges in terms of models, in terms of constraints, and when people will actually start designing in 3D. Over a number of years I’ve realized pathfinding definition is different for different people. You ask Riko and his definition is really visionary. I commend him for what he’s thinking. But then you talk to different people and pathfinding means different things. Still, if we really want to do the pathfinding we need to do what-if analysis between all these different scenarios, so that for a given system what is the most effective way to go? Is it 2.5D with this partition or 3D in this stack? There are so many variables. And that you can only effectively do with the right models, with the right constraints, with the known yields and reliability aspects, because that’s how you would do the performance, power, area, cost tradeoffs. Otherwise, there is no other way to get there. Four years down the lane I think we know a little bit more, but there are still a lot of unknowns we have to plug in before we can build the system together. I know of two standardization bodies that are focusing on this pathfinding effort. One is the Si2 perspective, which is the IC-level pathfinding. The other is the Sematech effort, which is more on the package pathfinding. At some point both of these have to marry together to make sure you are optimizing the entire thing.

SLD: How do EDA tool vendors work with the semiconductor manufacturing equipment suppliers?
Robertson: Mainly through our customers, so not well. We’re responsible for modeling the process, so it’s usually at the customer’s site where we’re getting an understanding of their lithography recipes, how it’s actually going to print, doing lots of test chips, etc. It’s not a direct cooperation, per se, because EDA to equipment alone doesn’t have the knowledge alone in terms of what do we want to print.

SLD: As 3D becomes a reality, what role will the foundries play in terms of integration? Who in the 3D ecosystem will take responsibility for the integration piece?
Chandrasekar: If you’re talking about true 3D, I expect foundries would be more involved and would take more leadership, but if it’s 2.5D it could be a combination of foundries and OSATs because there is a lot more integration and assembly in that aspect. But if it’s die on die, more wafer-level processing, I assume that foundries will be the leaders.
Bansal: Talking to the foundries and working with them, there are two distinct approaches. TSMC has taken a lead and ownership. They believe that yield and reliability are huge issues, whether it is 2.5D or 3D, because of the material property and many other issues of handling, breaking and warpage and everything involved. There is another camp that thinks either the business model of foundries or sending it to OSATs is viable. It’s not fully tested. It has been tested in 2.5D, but not 3D. It’s yet to be seen what’s going to happen, but whatever happens has to be cost-effective. It’s hard for us to predict what’s going to happen, and ultimately there has to be a way to figure out the reliability, the yield part of it, and then for every owner in that ecosystem to understand what that handoff looks like.
Robertson: I think it depends on whom you ask. If you ask the customers, they’re going to choose whatever is most cost-effective with the ability to triage when something goes wrong. ‘Do those two pieces exist? That’s what I need to find.’ The foundries are going to say, ‘I want to do everything soup to nuts, then I control it, and I’ll be responsible. If I don’t control everything, I’m not responsible for anything.’
Reiter: However, if you want to get the true value of 3D you have to mix a logic process, a CPU, a memory process, DRAM, an analog process, and you may want to do a gallium arsenide amplifier. I don’t know if one foundry will manufacture all these pieces cost effectively. One topic Sematech is spending a lot of effort on right now is thin wafer handling because the wafers are getting thinned to 50 microns. That’s as thin as one of your hairs. How do you get this thin wafer from whatever foundry to an assembly house and have it get there on time and without breaking. There’s a lot of development in regards to carriers, bonding/debonding techniques, and necessary shipping techniques, because I think eventually the foundries will ship to a consolidator who takes responsibility for the whole thing. And this consolidator will play the same role as Flextronics and board assembly people. I think that’s the only way.
Bansal: The business model will change and evolve. It has to for 3D to become mainstream. And it will be a mix. Whether it will be TSMC taking a giant step in extending itself—we will just have to see.
Reiter: What I hope is that the big IDMs that are left will set an example. That would leave the fabless industry no choice but to basically cooperate and do it the right way. We have a number of IDMs investing in this technology already.
Robertson: But they’ll also be assembling a package with best-in-class chips from several companies.
Bansal: We have to, in a sense, build a virtual IDM between the ecosystem players.

SLD: Do you see any roadblocks to 3D?
Chandrasekar: Even if it’s ultimately manufacturable, I’m not seeing any demonstrable cooling technology out there that can be cost-effective. There are different types of thin designs, all of which are mainly in R&D.
Reiter: 3D is a system design technology, but systems are application-specific. It’s no longer standard parts, standard memory, standard CPU. So it’s a system-specific, application-specific world. IBM will probably use water cooling, which was in high-performance servers, but if you have a cell phone just comparing application-specific options will be a big challenge. If you spin it further into the EDA world, system-level tools so far have not been very successful because every system house has its own system design tools and didn’t want to engage with the merchant EDA world. They were too slow and they didn’t understand the system-level world. There is a big opportunity now for the merchant EDA world to really show the system houses how to build their systems in 3D.