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Extreme Quality Semiconductor Manufacturing

Part 2: Future node ICs

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By Ben Tsai and Cathy Perry Sullivan

Across the full range of semiconductor device types and design nodes, there is a drive to produce chips with significantly higher quality. Automotive, IoT and other industrial applications require chips that achieve very high reliability over a long period of time, and some of these chips must maintain reliable performance while operating in an environment of temperature and humidity fluctuations, vibrations or other harsh conditions. Leading-edge semiconductor ICs with ≤5nm design nodes, gate all around (GAA) or other 3D architectures, and 1,000+ process steps require careful control of variability to achieve power and performance targets. Extreme quality semiconductor manufacturing innovations are essential to achieving variability and defectivity control, so that fabs can produce chips that meet strict reliability and performance standards.

This article focuses on the scaling, architecture and processing technologies for next-generation ICs that require more stringent quality control. The previous article in this series provided an overview of the automotive industry and the drive to produce ICs that meet automotive reliability standards.

Future Node Semiconductors
In order to support 5G, AI, data centers, edge computing and other industries, semiconductor manufacturers continue to develop ICs with increasingly complex architectures and smaller feature sizes. At the 5nm/3nm design nodes, a leading-edge logic chip may utilize an advanced finFET or GAA architecture (nanosheet or nanowire) and leverage EUV lithography (EUVL). Depending on design complexity, the cost to design a 5nm device is between $210 and $680 million,¹ while at the 3nm node the device design cost ranges from $500 million to $1.5 billion.² In addition, producing a new advanced node chip requires more than 1000 process steps. Each step involves process tools and materials that must meet rigorous quality standards to ensure that after all those process steps, the resulting chips are functional, and meet power and performance specifications. If something goes wrong at a single process step, it can cause lower performance, functional inconsistencies or outright failure of the chips, resulting in a tremendous financial loss for the fab.

To ensure that all process steps meet stringent quality standards, fabs have traditionally implemented defect and process-variation reduction and control strategies. By controlling process variation and defectivity, semiconductor fabs can obtain stable production and profitably produce devices at required power and performance targets. However, to support the architectural complexity, feature scaling, new processes and new materials in today’s leading-edge devices, it is necessary to achieve very tight tolerances for all types of variation and to eliminate ever smaller defect sizes. This drives the need for innovation in extreme quality control of buried features, materials, process equipment, EUVL and other areas.

Buried Features. 3D architectures are prevalent across advanced node logic and memory device types. On the logic side, 3D transistor structures began with finFETs, have persisted with the early versions of GAA nanowire or nanosheet FETs,³ and will continue with future logic device architectures, such as CFETs (complementary FETs) and full 3D logic. For 3D NAND memory devices, bit density increases as the number of vertical stacks gets higher. The number of stacks already exceeds 100, with double deck construction being used by many manufacturers. Producing these memory devices involves multi-layer deposition and high aspect ratio etches.

For both logic and memory 3D architectures, the process tools, wafers and materials used in each production step must meet strict quality standards. A process step running outside of established specifications can cause variations or anomalies in device parameters – for example, 3D NAND high aspect ratio contact hole shape or logic fin sidewall angle – which can then lead to poor device performance or failure. Monitoring the processes used to produce these 3D device structures is critical and requires measurement of buried features. Innovations in inspection and metrology technologies are needed to extract signal from these buried features. For example, new illumination sources can produce signal from defects or variations in high aspect ratio structures, while deep learning algorithms can suppress measurement noise or filter nuisance events from the inspection or metrology results. By developing effective process control methodologies for buried features, semiconductor manufacturers can then identify, monitor and control process issues associated with these complex 3D architectures.


3D NAND memory and 3nm nanowire transistor architectures create challenges for measuring and controlling buried features. (Image: KLA Corporation)

Materials Suppliers. Lack of quality in incoming materials (resists and other chemicals, wafers, etc.) can cause major process issues and financial harm, as evidenced by the loss of over half a billion dollars in revenue by a large semiconductor manufacturer due to photoresist quality issues.4 Material quality control is critical to managing yield and reliability at advanced design nodes.4

The most fundamental material supplied to fabs are the wafers. Substrate manufacturers currently implement outgoing quality control checks – for defects, surface roughness, flatness, etc. – before wafers are shipped to the fabs. And fabs perform incoming quality control checks on the wafers before they enter the process flow. This qualification strategy ensures that the starting substrates are free of the defects and surface quality issues that can affect the performance and reliability of the semiconductor devices built upon them. However, higher 3D NAND stacks and advanced logic architectures require starting substrates that meet ever stricter specifications for defectivity, surface roughness and flatness. These specifications drive the need for inspection and metrology systems that can detect smaller and smaller defects and accurately measure wafer flatness and nanotopography.

Materials other than wafers (e.g. resists) are also under increased quality scrutiny by semiconductor manufacturers. As design nodes become smaller, the particle size that can cause device yield or reliability issues shrinks, which means the materials used to produce ICs need to be free of ever smaller particles. Materials suppliers need to ensure that materials meet stringent quality requirements with every batch, after transportation, and after going through material delivery systems. Within the fab, high sensitivity unpatterned wafer defect inspection systems can be used for incoming material qualification by correlating inline defectivity data to different batches of materials, or by helping identify the root cause of materials-related defect excursions. However, semiconductor manufacturers are increasingly pushing materials qualification upstream to the materials supplier, requiring rigorous quality checks before a material becomes part of the fab’s process. Acquiring proof of qualification may go several ways. A supplier may need to invest in a cleanroom and inspection equipment to qualify their material. This may make it difficult for small material companies to survive, so it may make more economic sense to utilize independent qualification services. Or, it may be necessary to explore the possibility of developing an adequate qualification technique that doesn’t require an extensive infrastructure (cleanroom, etc.), yet mimics the fab environment.


Materials qualification using unpatterned wafer inspection can help fabs identify the root cause of a defect excursion. (Image: KLA Corporation)

Process Equipment Manufacturers. The move to smaller design nodes and complex 3D device architectures also affects process equipment. Film deposition tools, etchers, cleaning equipment, scanners, etc. are required to meet rigorous cleanliness requirements – gone are the days of building a process tool and just wiping it clean before it ships. Today, process tools must be qualified before they ship from the manufacturer, leveraging high sensitivity inspection and metrology systems to demonstrate that they meet strict standards for process uniformity and for the size and quantity of particles added per wafer pass (PWP). To meet these aggressive standards, equipment manufacturers need to address process tool cleanliness during R&D when the tool designs can be adjusted. Once installed in the semiconductor fab, process tool monitoring strategies need to be implemented so that engineers can promptly isolate and address process tool issues, thereby maintaining the high process quality necessary to produce advanced ICs.

EUV Lithography. The integration of EUV lithography, and the associated smaller design nodes, into IC production involves meticulous coordination and control of a new scanner, new reticles, and new resists and other consumables. Successful production using EUVL requires extreme quality control across all areas of semiconductor manufacturing, beginning with the reticle blank and reticle patterning. The higher resolution of EUVL means that reticle blanks and patterns need to be free of smaller defects, and the reticle patterns need to be precise to smaller design specifications. To support the smaller design nodes produced by EUVL, wafers need to be free of smaller defects, need to have less surface roughness, and must meet tighter specifications for wafer flatness and stress.

At the EUV scanner, quality control challenges arise from the fact that many layers will be exposed without a pellicle to protect the reticle during high volume manufacturing. Currently, EUV pellicles are not in use because of various challenges, including the fact that pellicle transmission is not high enough and would result in reduced throughput of the very expensive EUV scanners. This is the first time in ~30 years that the reticle will be “naked” during production, increasing the risk that particles and contaminants will land on the surface of the EUV reticle, causing defects to print on every die of the wafers. This means that IC fabs must take a more thorough approach to reticle re-qualification – for example, by combining direct reticle inspection with wafer print check to ensure all yield-critical mask defects are identified. This reticle quality control strategy, and any additional innovative techniques needed, will require new fab processes and process control flows compared to production using 193i scanners.


A wafer print check methodology is utilized along with standard reticle inspection to qualification EUV reticles in the semiconductor fab. (Image: KLA Corporation)

In addition, the stochastic nature of EUV lithography is at odds with the requirements of extreme quality semiconductor manufacturing, which typically demands fewer random variations. Stochastic effects create additional challenges for the inspection and metrology steps needed to qualify the EUVL process. For example, soft repeater defects print in some exposures and don’t print in others. Finding these defects at the wafer level requires an inspector with high sensitivity, a very high level of inspection coverage across the wafer, and intelligence to determine which detected defects are “repeaters” related to reticle issues. Furthermore, to achieve enhanced detection of stochastic defects, inspectors can utilize information from computational patterning software with stochastic simulation capability to efficiently characterize die regions susceptible to patterning failures. As a second example, line edge roughness (LER) due to stochastics affects the accuracy of metrology measurements, including CD uniformity and overlay error. Innovative techniques or new metrology and data analytic strategies will be required to help IC manufacturers effectively characterize, monitor and control LER and other stochastic effects.

EUVL is still in the early stages of high volume manufacturing. As it progresses, the industry will continue to develop novel strategies that will help fabs achieve needed quality standards for EUVL. In fact, it is possible that some leading semiconductor manufacturers will develop their own EUV-related manufacturing process flows, leading to proprietary methodologies for quality control.
Extreme quality semiconductor manufacturing plays a key role in helping semiconductor manufacturers produce the next generations of semiconductor devices. Manufacturing technology innovations focused on strict quality requirements across the entire supply chain will be critical for fabs’ successful ramps of smaller and smaller design node devices with increasingly complex architectures.

References
1. Gartner; LaPedus, “5nm Vs. 3nm,” Semiconductor Engineering, June 2019.
2. IBS; LaPedus, “5nm Vs. 3nm,” Semiconductor Engineering, June 2019.
3. https://news.samsung.com/global/infographic-reduced-size-increased-performance-samsungs-gaa-transistor-mbcfettm
4. https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&language=E&newsid=PGWQISTHTH

Cathy Perry Sullivan, Ph.D., is a technical marketing manager at KLA.



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