A new technical paper titled “Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs” was published by researchers at imec.
“We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous integration, achieving up to 12% higher operating frequency with 50% leakage power reduction in the memory macros,” states the paper.
Find the technical paper here. Published September 2024.
S. Das et al., “Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs,” in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, doi: 10.1109/JXCDC.2024.3468386.
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