Fix Processes, Then Silos

Jack Welch, former CEO of GE, was a big proponent of what he called a “boundaryless corporation.” It was a good sound bite, but it pales in comparison to former Intel CEO Andy Grove’s philosophy of working out of a cubicle, just like the rest of his staff.

While it’s great to have corporate buy-in for breaking down silos, which are vertically integrated, the real problem for semiconductor companies is more horizontal in nature. Below 65nm, and progressively so after that, power dictates everything. It’s a global issue in every design, and decisions become increasingly power-centric as the node numbers become progressively smaller.

There are several reasons for this. First, power budgets are fixed. There is only so long a battery will last between charges, and mobile device makers are gung-ho about adding more features, including better screens, while keeping the battery size the same or even smaller. One of the key reasons that Apple implemented a fan-out wafer-level package for its i7 application processor was that it takes up less space than a planar chip, so it could shrink the logic and still fit the battery. And in data centers, power budgets are measured in real dollars for powering and cooling server racks.

Second, heat—the byproduct of resistance, current leakage and dynamic power density (and frequently all three at once)—can migrate from one part of a chip to another because silicon acts as a conductor. So what looks like a separate design element in a device, perhaps even on a board adjacent to another part of a chip that has no processing, can actually be affected in unexpected ways.

And third, power needs to be addressed at every level of the design, with an understanding that if one segment exceeds its allotted power budget, that has to be made up somewhere else along the way. That includes more than just the chip hardware. It involves the software drivers, the package, the placement of the antenna, and even where the device will be used.

The same scenarios apply for security, as well, which is now a horizontal issue. It needs to be applied at every stage of a device. For connected devices, including cars, this has implications for all aspects of a design, including power and performance. Security also requires extra circuitry, and active security requires power. For cars, this is a huge system-wide problem (see fig. 1 below).

Fig. 1: Fifteen hackable areas in a car network. Source: Intel.

All of which leads back to the original point. Silos exist because they are the best way of getting a specific job done. They’re a way of dividing labor intelligently, and in a design flow it makes sense to segregate verification from layout because otherwise it would take many times longer to get a chip out the door.

The problem chipmakers are encountering these days is that power and security were add-ons to existing flows. At each new node for power, and each new market opportunity for security, those need to be horizontal processes on which the silos are built, rather than the other way around. It’s one thing to move around silos as needed. It’s quite another to revamp a fundamental business process. But as companies moving to 10nm and 7nm are finding out, shrinking features is becoming far more disruptive than just the transistor technology. It requires a change in some of the underlying processes, which are becoming too problematic to ignore.

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