GDDR6 PHYs: From The Data Center To Self-Driving Cars

GDDR memory is poised to expand to new markets, but challenges remain.

popularity

The demand for ever-increasing bandwidth has resulted in a growing interest in GDDR across a number of market verticals, including data centers and the automotive sector. As an example of the former, deep learning applications require ever-increasing speed and bandwidth memory solutions in the data center.

In deep learning and other emerging technologies, GDDR memory can help companies address modern bottlenecks inside the data center. According to Micron, GDDR offers a “huge step” in memory performance, making GDDR memory ideal for addressing the demands of data centers and modern networks. As IDG’s Agam Shah reports, GDDR6 could be used in network switches and routers, which in some instances are already equipped with GDDR5 memory. In addition, says Shah, GDDR6 will find a place in high-performance computers (HPC) for machine learning.

Outside the data center, demanding applications like self-driving cars will require a new generation of memory that supports increased bandwidth. For reference, current vehicles on the road are typically equipped with DRAM memory solutions that support a bandwidth of less than 60GB/s. Increasing this bandwidth should help enable autonomous vehicles to quickly execute massive calculations and safely implement real-time decisions on roads and highways. Indeed, Micron estimates that advanced driver assistance systems (ADAS) applications will ultimately demand 512GB/s – 1024 GB/s bandwidth to support Level 3 and 4 autonomous driving capabilities. As such, the company considers GDDR memory to be the “best alternative” to solving the reliability and temperature range constraints of the automotive industry.

Understanding GDDR6 PHY design challenges
Perhaps not surprisingly, the PHY is one of most important pieces of IP on an application-specific integrated circuit (ASIC). With GDDR PHYs providing a maximum bandwidth of up to 64 GB/s, it is critical for ASIC designers to ensure that a device isn’t affected by signal integrity issues. Put simply, signal integrity (SI) is a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional SI issues include jitter, ringing, crosstalk, ground bounce and power supply noise.

There are a number of factors that can negatively influence SI and cause errors or even system failure, including higher bit rates and extended distances. If not properly addressed during the design stage, SI issues will likely cause the GDDR PHY to become unreliable and malfunction in the field. To overcome potential SI issues, design teams should make extensive use of advanced tools such as IBIS-AMI modeling, thereby enabling rapid, accurate and statistically significant simulation of a customer’s GDDR6 PHY.

Beyond simulations, GDDR6 PHY engineers should design highly-programmable circuits, debug interfaces and utilities that enable customers to easily collate important analog and digital information. In addition to highly-programmable circuits, one of the most important aspects of GDDR PHY design is validating silicon with a test chip. To be sure, there isn’t a true substitute for taping out a test chip, verifying it in the lab and enabling first-time-right silicon in a timely manner. This is precisely why engineering teams should comprise a range of in-house experts that participate in all stages of the GDDR6 PHY design. These include package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists.

Conclusion
The insatiable demand for increased bandwidth has prompted a growing interest in GDDR across a number of market verticals, including the automotive sector and data centers. With GDDR PHYs providing a maximum bandwidth of up to 64 GB/s, it is critical for ASIC designers to ensure that a device isn’t affected by signal integrity issues. An experienced engineering team can help facilitate both SI and timely test chip tapeouts by leveraging advanced modeling, along with highly-programmable PHY circuits, debug interfaces and utilities.



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