Going Vertical?

Scaling and packaging emerge as key discussion points across the semiconductor industry.


The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform density scaling strategies at a SEMICON West 2017 TechXPOT session on the topic (“The Economics of Density Scaling” on Thursday, July 13, 2:00pm-4:00pm).

To get a preview of topics that have captured the interest and attention of the industry, SEMI interviewed some of the confirmed speakers (from Applied Materials, Imec, Intel, Rudolph Technologies, and Synopsys) at the session. (Click here for a complete list of speakers and the full agenda for the session.)

Packaging as a driver for next-gen device performance
Gurvinder Singh, director, Product Management, at Rudolph Technologies, told SEMI that scaling the package will drive the performance of next-generation devices. “Higher density interconnect and scaling in the front-end of device manufacturing is pushing packaging technologies’ design and process control requirements beyond the current standards implemented,” said Singh. “Dimensions of some redistributed layers (RDL), through-silicon vias (TSVs) and other components have reached the size where sub-micron sensitivity is required for reliable defect detection.”

Singh noted that the industry has already driven RDL lines/spaces to 5µm and he expects a number of customers to further drive this down to 2µm lines/spaces by the end of the year. “Conventional techniques for inspection and metrology employed in the traditional packaging world are running into limits requiring the need for a novel approach to new solutions or transferring some front-end solutions to the advanced packaging arena in a cost-effective manner.”

As greater numbers of known good dies (KGDs) are used in more advanced packaging methodologies, Singh explained that new process control steps with tighter tolerances have been added to deal with the increased concern about the economic implications of yield loss. He cited the addition of kerf control check after saw (see Figure 1).

Fig. 1: Kerf metrology: what’s measured. SOURCE: Rudolph Technologies

“Customers are requiring a closed-loop system that records the conditions of the dicer during the saw process and correlates it to inspection (e.g., die chipping and cracking) and metrology (e.g., kerf margins and offset),” said Singh. “The ability to use the data to predict system issues and halt the system to prevent any further yield loss is where our customers are heading.”

The company is pursuing a strategy of providing solutions for each system integration process flow that include inspection, metrology, lithography and software. “Data is the key ingredient in understanding the impact of integration of these solutions on manufacturing and packaging,” said Singh. “Fan-out panel-level packaging (FOPLP) is an excellent example where you see these different systems and solutions integrating.” According to Singh, FOPLP requires key inspection and metrology steps including:

1) kerf control

2) die shift measurement (i.e., correcting die placement systems and feeding forward to lithography systems)

3) overlay and critical dimension measurement

4) polyimide/photoresist or metal residue detection

5) RDL defect detection (open/short/nick)

6) RDL metrology (width, height), bump height and coplanarity.

Singh explained that gaining a handle on these intersecting disciplines requires the ability to track known good dies from different wafers and technology nodes to reconstituted panels and the final packages. “Our customers are interested in analyzing the complete supply chain data essential for smart manufacturing. Solutions are required to enable the partitioning of data by die, package, and wafer, and centralizing electrical, metrology and defect data in a single source.” This is where the concept of “Big Data” that is generated from different fabs, lines, and geographical locations comes into play. “Successful solutions turn this data into information and the information into insight.”

Looking beyond 5nm, Singh observed that while a few key players will drive traditional scaling, there will be a shift to scaling of the package. “Package scaling will help address the need for lower power, lower latency, and lower cost with high performance, which will be difficult to achieve through CMOS scaling,” said Singh. “The industry will combine components and technologies from the smartphone ecosystem to create a virtually limitless variety of next-generation devices.” He expects advanced packaging to play a key role by leveraging both homogenous and inhomogeneous integration.

Expanding on the concepts noted above, Singh cited the example of system-in-package (SiP) solutions that require the “reconstitution” of multiple heterogeneous die on a substrate in wafer or panel format. “Process challenges including lithography, inspection and metrology are mainly attributed to the rebuilt accuracy of the substrate,” Singh told SEMI. “Die shift can be induced during placement and it can be further affected during the molding process.” He explained that inspection and metrology systems should have the capabilities to measure, analyze and report to correct the die position errors at the pick-and-place systems. “Additionally, the systems should be capable of calculating and feeding forward the correction to the lithography systems. This enables the lithography process to achieve the best possible process window given the incoming die placement errors improving overall yield.”

Designers avoid unnecessary risks
Along with contemplating the technical challenges in going from 7nm to 5nm, Jamil Kawa, a Fellow at Synopsys, told SEMI that the dominant factors in determining whether a new node is adopted or not are still more or less the same: power, performance, area, readiness, cost, and yield. “Designers have to see in the new node an advantage they cannot attain today with an existing node/design,” observed Kawa. “Otherwise, a designer will be taking an unnecessary risk.” He explained that, from an EDA perspective, the deployment of EUV for critical layers will be the main differentiating feature. “EUV deployment reduces the number of masks and improves the design window (i.e., tighter tolerances), and that is a big thing, which also leads to smaller area and to better yield through reduced misalignment-driven variability.” While he allows that performance will always be important, it is no longer the main driving factor in the decision to adopt those nodes.

Similarly, with respect to the economic drivers that will enable the industry’s movement to 7nm and 5nm, Kawa explained that from the EDA/design perspective, performance specifications, though important, will not be the prominent determining factor. “Other design consideration stemming from the use of new materials (e.g., cobalt, tungsten) and their impact on reliability, especially electromigration, are important,” said Kawa. “Similarly, the impact of the use of new process techniques and of EUV on overall design parameter variability is important.”

Given that the industry has been pursuing scaling methodologies such as 3D packaging and vertical architectures before moving to more exotic strategies, Kawa told SEMI that the path or paths taken by industry players comes down to economics, practicality, and power consumption. “Advanced nodes are expensive, and most applications do not call for advanced nodes,” said Kawa. “For most functionalities, there is a technology sweet-spot that accommodates functionality, performance, reliability, and availability.”

He cited FLASH technology at 45nm and 65nm as an example. He went on to note that 3D integration has matured significantly in the last 8 years. “Therefore, 3D, or more accurately, 2D/2.5D integration with various kinds of interposers (passive vs. organic vs. silicon) is the way to go and it enables heterogeneous integration utilizing the best of all worlds.” He also believes that 2.5D integration can have an added advantage in achieving lower power and enabling the integration of HBM memory solutions.

Relative to the EDA challenges that lie ahead, a concern of An Steegen, EVP of Semiconductor Technology and Systems, at Imec, is being able to do place and route efficiently given the difficulty in continuing track scaling. “The need for an effective, truly “3D” EDA design flow is required to support the designers of future electronic systems to move from the traditional 2D-SoC homogeneous technology design flow approach to an effective 3D-SoC heterogeneous design flow,” explained Steegen.

Going forward, Steegen emphasized that 3D integration technology covers a broad range of technologies, allowing for integrating devices at a broad range of interconnect densities. “From hundreds of microns pitch at the package level, to hundreds of nanometers at the device level, 3D integration intersects the electronic system integration flow at multiple levels of the interconnect hierarchy,” said Steegen. “This does not happen in a sequential way (from coarse- to fine-grain scaling), but happens rather in a concurrent fashion, at all levels of the interconnect hierarchy where 3D integration technologies appear.”

Examples she highlighted include package-on-package stacks used for mobile processors; silicon interposers for FPGA and GPUs; die-to-die stacks for DRAM, wafer-bonded image sensors, and 3D device-level stacks, such as those used for the latest 3D-NAND technology. “The introduction of these 3D technologies depends on the requirements at the system level for higher interconnect bandwidth and emerges when the approach is economically viable. This evolution occurs at the same time as the device scaling and device performance improvement.” She further notes that the evolution of new technologies for high-performance, low-power, novel memories, and the like, increases the need for high-density 3D integration technologies to build heterogeneous “3D systems-on-chip.”

Tradeoffs for scaling beyond finFETs
Mike Chudzik, senior director of Technical Projects, Transistor and Interconnect Group, at Applied Materials, told SEMI that, while economics is a large factor in driving scaling, the primary drivers are process readiness and performance gained by these changes. “For instance, other vertical architectures beyond finFET promise to improve device density, but are still in R&D,” said Chudzik. “Monolithic 3D devices are in the same category — they have huge potential, but the performance of the upper levels are impacted by the lower thermal budgets required to fabricate them, so further industry development is needed.”

Chudzik sees the 7nm node as being an assertive scale of 16/14nm with aggressive pitch scaling. “With the exception of the introduction of cobalt at the contact fill level, I don’t expect major materials or architecture inflections at the 7nm node,” Chudzik told SEMI. “And 5nm is shaping up to possibly have a materials change to SiGe or an architecture change to hGAA as an example, but it’s too early to make that call.”

Sizing up the role that patterning technologies will play in chip makers’ decisions, Chudzik explained that economically, every foundry/OEM has a unique cost structure, so the economic drivers will be different for each. “Some foundries might choose to wait for EUV to be further along before adopting 7nm, while leading foundries won’t wait and will adopt patterning solutions, such as SAQP, to get to 32-34nm and 35-40nm for the fin and M1 pitches, respectively.”

He envisions the role that cell phone manufacturers will play as pushing the foundries to yearly silicon refresh dates, which will therefore drive the new nodes. “These new nodes may involve any number of small or large changes in order to provide some sort of power, performance, area and cost advantages of the previous node.” Going from 7nm to 5nm, Chudzik suggested that pitches of sub-40nm will require SAQP or EUV. “Both of these mean more cost, however they are at slightly different levels of readiness. So, perhaps SAQP is the opening act to 7nm, with EUV a follow-on for cuts/vias, and then by 5nm for more levels.”

Moore’s Law not dead yet
Mark Bohr, senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration, at Intel, as one would expect, is enthusiastic about the continuance of Moore’s Law. “If you dispense with sometimes misleading node names and use a quantitative transistor density metric, you will see that we continue to deliver improvements in transistor density at a rate of ~2x every 2 years,” Bohr told SEMI (Figure 2). “Intel’s 10nm technology is estimated to provide close to double the transistor density of what others are calling 10nm.”

Figure 2. Hyper scaling on Intel’s 14nm and 10nm provides low cost per transistor (CPT). SOURCE: Intel

While acknowledging that the semiconductor industry has long since left any type of predictable roadmap, Bohr observed that each new generation struggles with difficult density/cost/performance/power tradeoffs. “In the future, we will see more examples of heterogeneous integration techniques where different process technologies are combined in some integrated way to meet the sometimes divergent needs of compute/communication/memory circuits,” said Bohr.

Regarding the technology considerations that will drive economic decisions as scaling is continued, Bohr noted that most new patterning options (e.g., double-patterning, quad-patterning, EUV) come with added process cost and complexity. “These new patterning techniques need to be used judiciously, where they provide the most density improvement for the added cost,” said Bohr. “Layout design rules also need to strike a balance between providing the best density and being easy to design, because the cost of design is also increasing.”

To hear these speakers and more at SEMICON West 2017, attend the TechXPOT session “The Economics of Density Scaling” on Thursday, July 13, 2:00pm-4:00pm. Click here for a complete list of speakers and the full agenda for the session.

To register for SEMICON West 2017, click here.


Leave a Reply

(Note: This name will be displayed publicly)