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Hardware Implementation Of A Random Gumber Generator On A FPGA

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A new research paper titled “FPGA Random Number Generator” was published by a researcher at Johns Hopkins University.

According to the paper’s abstract:
“This paper offers a proof-of-concept for creating a verilog-based hardware design that utilizes random measurement and scrambling algorithms to generate 32-bit random synchronously with a single clock cycle on a field-programmable-gate-array(FPGA).”

Find the technical paper here. Published August 2022.

Author: Jacob Hammond, Johns Hopkins University. arXiv:2209.04423v1



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