Heterogeneous Integration: Exposing Large Panels With Fewer Shots

By John Chang, with Corey Shay, James Webb, and Timothy Chang

The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration is one tool helping accomplish these gains by combining multiple silicon nodes and designs inside one package.

But as with any technology, heterogeneous integration, and the fan-out panel-level packaging that often enables it, comes with its own set of unique challenges. For starters, package sizes are expected to grow significantly due to the number of components making up each integrated package. The problem: these significantly bigger packages require multiple exposure shots to complete the lithography steps for the package. Adding to this, multiple redistribution layers (RDL) may cause stress to both the surface and inside of the substrate, resulting in warpage. And then there is the matter of tightening resolution requirements and more stringent overlay needs.

Fig. 1: The path to heterogeneous integration. (Source: Cadence)

The trouble with stitching

Heterogeneous integration requires the integration of multiple chips into a single package, the size ranging from 75mm x 75mm to 150mm x 150mm or even larger packages for future applications. However, for an advanced packaging stepper with a limited exposure field of 59mm x 59mm, multiple exposure shots are needed to complete one of these larger package sizes. Known in the industry as “stitching,” this method requires multiple reticles and has low throughput. Not surprisingly, this increases costs.

Fortunately, there is a solution to address these stitching challenges. By increasing the stepper field size to more than 150mm x 150mm, the need for stitching is eliminated and throughput increases significantly. While it takes 64 shots for current advanced packaging steppers with an exposure field of 59mm x 59mm, a stepper with an extremely large exposure field can completely expose a 510mm x 515mm panel with just four shots, eliminating the need for image stitching (figure 2).

With stitching no longer necessary, a barrier to increase throughput is removed.

Fig. 2: The layout of an extremely large exposure field (250mm x 250mm) and a regular exposure field (59mm x 59mm) on a 510mm x 515mm panel. With the extremely large exposure field, a panel can be completed with just four (4) shots; with a current large exposure field, a panel requires 64 shots to complete.

Warpage and resolution

The addition of multiple redistribution layers (RDL) to the substrate may cause stress to both the surface and inside of the substrate. The possible result of these stresses: warpage and formation change. If the substrate suffers deformation from high pressure, high temperature, or other process steps, this deformation can cause a pattern shift and affect the overlay results in the lithography process on large-format panels. If left uncorrected during the exposing process, these factors can result in serious overlay errors.

Adding to these challenges, advanced integrated circuit substrates (AICS) RDL layers will require a resolution of 3µm, eventually moving toward 1µm.

Let’s take a look at an example of how to resolve these issues. In our experiment, we used a stepper with an extremely large, fine-resolution exposure field. In addition, we selected a copper seed wafer with 10µm-thick dry film resist to determine the resolution performance of the lithography system. As seen in figure 3, in only four shots the stepper demonstrated a line/space resolution of 3µm, while offering a depth of focus up to 60µm.

Fig. 3: Extremely large exposure field, fine-resolution lithography system resolution performance: 1. Copper seed wafer cross-section image of 3µm line/space with 10µm thick dry film resist, which is a 1:3.3 aspect ratio. 2. Isolated and dense area resolution results of 3µm, 3.5µm and 4µm line/space. 3. Bossung curve of 3µm line/space with a 10µm-thick dry film resist. The X axis is focus (µm), and the Y axis is CD (µm). A 60µm depth of focus is observed in 3µm line/space with 10µm-thick dry film resist.

To test the overlay performance of the lithography system, we selected a 510mm x 515mm glass panel with a 1.4µm liquid resist. The test vehicle was run with a site-by-site correction method at four shots per panel to build the second layer. We then checked the overlay error between layer 1 and layer 2 to determine the overlay performance. The overlay error was determined by reading the location of overlapped verniers. Each exposure field contains 3 x 3 measurement points, and 2 x 2 shots per panel were measured to determine the overlay performance of the lithography system.

According to our overlay performance analysis, a single reflective alignment system (RAS) camera demonstrated a deviation |X| mean +3 sigma of 0.91µm and a deviation |Y| mean +3 sigma of 0.91µm. These numbers indicate an extremely large exposure field, fine-resolution lithography system can achieve the aggressive overlay number of less than 1µm that will be required for future advanced packaging applications.

In the next few years, with resolution becoming smaller and overlay budgets growing tighter, overlay control will become more important in heterogeneous integration. Fortunately, there are ways to achieve these aggressive overlay requirements.

In a future blog focusing on the heterogeneous integration challenges in fan-out panel-level packaging, we hope to show how to successfully use an extremely large exposure field, fine-resolution lithography system to identify error terms and distortion components in an AICS panel and correct these to achieve good overlay. Proper error and distortion corrections, zone solution correction, and additional compensation are key to achieving the best overlay numbers for high-volume manufacturing.

Corey Shay is a senior applications engineer at Onto Innovation.
James Webb is director of technology at Onto Innovation.
Timothy Chang is senior director of applications at Onto Innovation.