High-Performance P-Type FET Arrays With Single-Crystal 2D Semiconductors And Fermi-Level-Tuned vdW Contact Electrodes

A technical paper titled “Fabrication of p-type 2D single-crystalline transistor arrays with Fermi-level-tuned van der Waals semimetal electrodes” was published by researchers at Ulsan National Institute of Science and Technology (UNIST), University of Pennsylvania, Institute for Basic Science (IBS), Sogang University, and Changwon National University.

Abstract:

“High-performance p-type two-dimensional (2D) transistors are fundamental for 2D nanoelectronics. However, the lack of a reliable method for creating high-quality, large-scale p-type 2D semiconductors and a suitable metallization process represents important challenges that need to be addressed for future developments of the field. Here, we report the fabrication of scalable p-type 2D single-crystalline 2H-MoTe₂ transistor arrays with Fermi-level-tuned 1T’-phase semimetal contact electrodes. By transforming polycrystalline 1T’-MoTe₂ to 2H polymorph via abnormal grain growth, we fabricated 4-inch 2H-MoTe₂ wafers with ultra-large single-crystalline domains and spatially-controlled single-crystalline arrays at a low temperature (~500 °C). Furthermore, we demonstrate on-chip transistors by lithographic patterning and layer-by-layer integration of 1T’ semimetals and 2H semiconductors. Work function modulation of 1T’-MoTe₂ electrodes was achieved by depositing 3D metal (Au) pads, resulting in minimal contact resistance (~0.7 kΩ·μm) and near-zero Schottky barrier height (~14 meV) of the junction interface, and leading to high on-state current (~7.8 μA/μm) and on/off current ratio (~10⁵) in the 2H-MoTe₂ transistors.”

Find the technical paper here. Published August 2023.

Song, S., Yoon, A., Jang, S. et al. Fabrication of p-type 2D single-crystalline transistor arrays with Fermi-level-tuned van der Waals semimetal electrodes. Nat Commun 14, 4747 (2023). https://doi.org/10.1038/s41467-023-40448-x

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