A new technical paper titled “Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap” was published by researchers at Northeastern University, Korea Institute of Science and Technology, Gyeongsang National University and others.
“Here, we prepare highly dense and vertically aligned sub-5 nm silicon nanowires with length/diameter aspect ratios greater than 10,000 by developing a catalyst-free chemical vapor etching process. We observe an unusual lattice reduction of up to 20% within ultra-narrow silicon nanowires and good oxidation stability in air compared to conventional silicon,” states the paper.
Find the technical paper here. Published June 2022.
Gao, S., Hong, S., Park, S. et al. Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap. Nat Commun 13, 3467 (2022). https://doi.org/10.1038/s41467-022-31174-x. Open access https://www.nature.com/articles/s41467-022-31174-x#rightslink.
Related Reading:
Big Changes In Architectures, Transistors, Materials
Who’s doing what in next-gen chips, and when they expect to do it.
Impact Of GAA Transistors At 3/2nm
Some things will get better from a design perspective, while others will be worse.
The Increasingly Uneven Race To 3nm/2nm
An emphasis on customization, many more packaging options, and rising costs of scaling are changing dynamics across the industry.
Leave a Reply