Wafer-level test results for PMOS transistor degradation rates under NBTI stress, using a new reliability monitoring suite.
We have developed a new reliability monitoring suite, within a proprietary IP block that we call a CV Core, with aging sensors embedded in the product layout and testable through the product I / O interface. We illustrate the application of the sensor suite with an example of the PMOS NBTI monitor, testable at the wafer level during product electrical wafer sort (EWS), as well after packaging at final test or during burn-in. During EWS, the wafer-level stress test can be used to identify a marginal chip, help material dispositioning for burn-in, or support additional grading for chiplet matching for multi-chip modules. The aging sensors can also be used during the chip lifetime to monitor the device wear-out and alarm users about abnormal silicon aging rates against target mission profile. In this work, we show the wafer level test results for PMOS transistor degradation rates under NBTI stress, within wafer variability, and correlation of degradation rates between sensors stressed under different conditions.
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