Inside The Package

A candid discussion with a top exec at ASE about the future of packaging, stacked die, package-on-package, and how the market will shake out between foundries and OSATs.


By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house.

SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for years, we’ve been waiting for a major shakeout in the sector. When will we see the shakeout?
Rice: It will eventually happen. It’s hard to say when this will take place. In packaging, the top subcontractors are fairly broad-based in the markets they serve. There are only so many companies in this space. Meanwhile, the smaller subcontractors generally offer niche technologies. But some of smaller subcontractors have specialized tooling and unique packaging. That type of thing is difficult to replicate, especially when the cost is very low and there is fully depreciated equipment involved. Those things tend to keep the smaller subcontractors in place for a long time.

SMD: Where are we in the business cycle in IC packaging?
Rice: In packaging, I wouldn’t say business is slow, but it’s not strong. As you know, the global semiconductor market has been somewhat tepid. The products that are selling in the market are the iPhone, iPad, Samsung Galaxy and things like that. If you are designed into one of those products, you are doing okay. If you are not, you are probably struggling.

SMD: Where are we in 3D TSV technology?
Rice: A lot of the fundamental assembly and interposer work is progressing. There are still challenges. Yields are definitely going to be a challenge. The question is how you manage yields. Then, you have test challenges. I personally feel pretty comfortable about the progress on that front. Overall, 3D TSV technology is not ready for high-volume production. Memory seems to be a limiting factor. The memory availability on these larger stacks is going to define when these 3D products will get launched.

SMD: When will we see stacked die in mobile phones?
Rice: In mobile, we’d love to have 3D. But it’s not going to be ready for a while, probably because of memory stack availability. Plus, the big OEMs hold a lot of the cards on when 3D might potentially be used and deployed.

SMD: For some time, ASE has talked about providing silicon interposers and 3D technology. What is the latest at ASE?
Rice: We have an interposer technology that we’ve promoted. We are not sure what the market acceptance is. Poking holes in silicon is mostly a foundry business. We can do some of it. We can do very simple dry etch processes on a die, via last and very course technologies. But for really fine-pitch 3D ICs or 2.5D interposers, that’s really a foundry type of business.

SMD: So ultimately, what role will OSATs play in the 2.5D and 3D market?
Rice: We will do the backend integration processes.

SMD: As you know, TSMC is offering a turnkey solution in 2.5D/3D. How do you see that playing out?
Rice: The guy that does the integrated solution will probably end up with a low mix, meaning a smaller number of device types, but probably at high volumes. My rationale behind that is very simple. Foundries have a common process platform. They are not tweaking their processes a lot. In other words, they have a lot of different devices that go through the same process.

SMD: What challenges will TSMC face doing the backend processes?
Rice: They must deal with having a toolbox with various interconnect technologies, and how you put it together, and how you manage that. It’s something we do day in and day out. And they don’t.

SMD: There is still a lot of activity in traditional packaging. What are some of the trends at the high end?
Rice: There are different markets. The advanced wafer node market has been driven by PCs, graphics, CPUs as well as servers. Typically, you will see larger packages with a ton of pins. For example, you have flip-chip BGA. We’re talking about pin counts in the thousands. This is where you will see the eventual introduction of 2.5D interposers.

SMD: What about other packaging markets?
Rice: On the cost-performance side, we look at this as the consumer market. In this market you have simple wirebond BGA and QFN. QFN is an industry word for quad-flat no-leads. The leads are basically on the bottom of the package. On the systems integration front, this is where you start seeing a lot of multi-die integration. For instance, you have PoP, or package-on-package. In PoP, you have a logic processor on the bottom and a memory on top. In PoP, we are seeing anywhere from 500 to over 1,000 pins. These are typically for mobile devices.

SMD: Where is PoP heading?
Rice: PoP morphs into different approaches as we try to make it thinner. We want to keep that down to 1mm or lower. While we are trying to make it thinner, we are also doing embedded technologies. You might embed a passive or active in the actual substrate itself. You might put capacitors as close as possible to the I/O of the die. You might embed a simple active component such as a power management device. You may want to embed components close to the processor, which can help with the power control and supply. In embedded PoP, you’re trying to get as much silicon packed in a particular volumetric area on the package.

SMD: What are the challenges with embedded PoP?
Rice: It’s disrupts the supply chain on how substrates are made. The substrate suppliers have not had that kind of capability yet, such as handling bare die or handling passive components inside their lines. In addition, if the interconnect is not robust or the yield is bad on the silicon, you throw away the whole substrate.

SMD: Is the embedded PoP shipping now?
Rice: Probably soon.

SMD: Another next-generation PoP is fan-out. Where is fan-out going?
Rice: In fan-out, you could make a really thin package. If you can get your signals from the bottom to the top of the package, and then put another memory package on top, you can get a fairly thin solution. It’s on our roadmap. We’ve had a fan-out production line for a long time. We were one of Infineon’s early fan-out licensees. We’re manufacturing on a 200mm format. To go to 300mm is a large investment. STATS ChipPAC has 300mm capability. We choose not to chase 300mm at this time.

SMD: What are the challenges with fan-out?
Rice: In terms of making holes through that package, we found it to be quite difficult. It’s a different type of mold compound. You have to use alternative means to get the signals up to the top. Secondly, as far as the package infrastructure itself, it is a wafer-level package. Wafer-level package infrastructure is quite different than regular package infrastructure. The investment level is much higher. So, you have to calculate your payback.

SMD: Is that why ASE is pursuing embedded PoP?
Rice: Potentially, you can embed a die into a PCB in a panel format. That could be more cost-effective than using a wafer format. It’s a lower cost infrastructure.

SMD: What else is going on in packaging in mobile phones?
Rice: With mobile phones, the board technology is extremely dense. The PCB is a high-density, built-up substrate. It can also handle very fine-pitch interconnect. You are also placing wafer-level CSPs on top of the substrate, which are essentially bare die. So, the mobile phone platform is essentially becoming a big package. Your cell-phone motherboard, in a sense, is a multi-chip module.

SMD: Is that driving the demand for wafer-level CSPs?
Rice: In most cell phones, a very high percentage of the components now are wafer-level CSPs. These components used to be housed in packages like BGA, QFP or QFN. Now, they are moving towards wafer-level CSPs, which are mounted to the motherboard. That’s why you’re seeing the wafer-level CSP growth rate going so high.

SMD: Will the cell-phone PCB ultimately become the package?
Rice: If you look at all of these bare pieces of silicon that are going on the mobile phone motherboard, it’s almost like a big package. But I don’t see it all becoming one big package for a while. There is not a single chip that does everything in a phone. There are far too many diverse technologies, features and IP in a cell phone. For example, you will continue to see discrete application processor packages.

SMD: What else is going on in multi-die packaging?
Rice: The industry has shipped multi-die packages for decades. In an early and simple configuration, you saw two die in a PDIP or even two die in a transistor package. We are doing a lot of multi-die packaging today. We are literally doing hundreds of millions of units per month. Today, we see high-density, flip-chip being used with a wirebond part stacked on top of it. It is all molded into one package. We see a lot of wirebonding packaging, where you have a lot of multi-die in the package. There are a lot of die-to-die wirebonds. So, you get into some exotic layouts in how you do your wirebonding.

SMD: So where is IC packaging headed?
Rice: The packaging portfolio will continue to expand. We will see more packaging technologies that are different and unique.

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