Integrated Photonics (Part 2)

Semiconductor Engineering sat down to discuss the status of integrated photonics with Twan Korthorst, CEO for PhoeniX Software; Gilles Lamant, distinguished engineer for Cadence; Bill De Vries, director of marketing for Lumerical Solutions; and Brett Attaway, director of EPDA solutions at AIM Photonics, SUNY Polytechnic Institute. What follows are excerpts of that conversation. Part one can be found here.

Fig. 1: Photonics panel. Photo by Brian Bailey

SE: Is cost the big headwind for integrated photonics?

Korthorst: There is a successful Dutch company where cost is not that important. They are involved with fiber optical sensing. They have been active for 25 years delivering very high sensitivity strain and stress sensing fiber. You can put the fiber into a building or in an airplane wing or in the blade of a turbine and you can measure strain and stress by optical means. The readout mechanism was a cubic meter, and that unit is 100,000 Euros. This company switched to an integrated photonics solution, which is now much smaller and costs only 1,000 Euros. Suddenly it opens up many more potential applications. This company is exploding. By shrinking the form factor and bringing the price down, they have changed the industry. However, for that application, 1,000 Euros is okay. For other volume applications, we need to bring the cost down even lower. The only answer to that is more volume. What we have seen in CMOS, or solar panel fabrication, that volume drives cost down.

Attaway: That is why the U.S. government said, ‘Lets push some money into this to bring the cost factor down by increasing reliability and yield.’

Korthorst: Yes, AIM in the U.S. In Europe there are some similar programs where they promoted this technology by lowering access barriers, and this is attracting more people to the ecosystem, driving volume and innovation.

Attaway: Being on the wafer, it all comes down to die costs, and we can beat that down pretty good. One of the highest costs is packaging. The cost of being able to handle optical interfaces on a package is different from the electronics world. That is the number one target today. At AIM we will be targeting that hard for the next few years, and hopefully we can show some advancement that is repeatable and applies to high volume.

SE: Have we managed to bring the laser on board yet?

Korthorst: A laser needs III/V materials and they are not very compatible with silicon. There are different ways in which people have been developing technology to bring a laser very close to silicon, and there are several solutions out there now in commercial products. So you could say it has been solved from an economics perspective. Can it be improved? Does it need to be improved? Yes. But there are different ways to tackle the light source integration or interfacing with the silicon.

Lamant: Packaging is the bigger problem, but that is part of the problem of getting the light in.

Attaway: Yes, the definition of packaging could include getting the light source into it. At AIM, we have a couple of directions – one is heterogeneous integration of different die using an interposer. You can design a laser going next to the photonic chip and integrate them on a passive interposer. It enables the laser to be close to, and tightly integrated with, the photonics chips. Then there is another project that grows lasers directly on silicon photonics chips via epitaxial growth growth and processing of III-V materials on the silicon wafer. We’re working (at AIM Photonics) to make this on-chip laser technology cost effective and highly manufacturable.

De Vries: It goes hand in hand with the packaging. They are almost a combined problem. You can build the wafers—multi-chip, two different wafers bonded together. But at the end of the day integration is the key, putting it into a package and being able to assemble that reliably is a bigger problem today. How do I get light in and out of that package? How does the industry develop standard packaging that is scalable, and which becomes cost-effective where the cost of the water is pretty predictable but the package is custom and orders of magnitude more expensive? That becomes restrictive. Then there is testing. One of the things that makes CMOS so advantageous is the fact that nobody has to touch it. It is very reliable. Optics is not quite there yet. There are lots of people kicking the tires on ways to automate it. The AIM organization has a team that is spending time researching the test and automation side of things. That is a huge challenge. Once the industry says, ‘Okay, there is a standard set of packages to put these things together and I can get light in an out in a handful of reliable ways,’ then you will start to see these applications become more scaled. That’s not only the functional applications. Now I am using these integrated photonics devices for a whole bunch of different things because it is just another building block in my system.

Korthorst: It is more like digital electronics, where you can have self-test. But photonics is more like analog or RF electronics, which is more sensitive to process variation. When you look at waveguide materials today, silicon photonics uses silicon to construct the waveguides, but you see that people are adding silicon nitride layers as waveguide material which is still the same platform, but the waveguide is different. It can be transparent for visible light and has lower losses and is an integral part of the silicon platform but in addition, most integrated photonics circuits in the field today are based on indium phosphide. There you have the laser integrated. But the promise of silicon and CMOS is that you can bring down the cost more than for other materials, and you have the infrastructure in place that is proven and validated for high-volume applications.

Lamant: Phosphide wafers are two to three inches. CMOS wafers are much bigger—200mm or even 300mm. That is very relevant for photonics. FinFETs – some of the issues they had with line edge roughness – those are very relevant when you move them onto a waveguide, which may be large in size but very sensitive to everything that happens on the edges. So there is a big possible leverage of the technology that has happened for the CMOS fab to refine the processing capabilities for finFETs and advanced nodes, and which can be applied to photonics. This is directly applicable to making photonics reliable and predictable.

Korthorst: The expected lifetime of a communications link is 25 years. Improving assembly and packaging is a big cost driver. In the data center, they are telling the photonics industry that they will replace everything every four or five years. So from a lifetime perspective, don’t try to bring long-haul standards into the datacenter. If one transceiver fails, there is so much redundancy in the data center network that it can just be replaced. Reliability means bringing down the standards that provide a solution that is more cost-effective. There are several companies working on bio-sensing one-time use products. They have a tiny bit of photonics inside and you use it once and throw it away. This is completely different than long haul.

SE: Photonics chips are huge compared to digital devices. What fabrication technologies are people using today?

De Vries: There are no nodes in photonics. There is no monolithic integration. It comes back to how you define integration.

Attaway: Heterogeneous multi-die integration is what makes sense. The photonic processing in a fab is a quarter of advanced CMOS processing. When you get to high volume, the cost may be a wash.

Korthorst: There are more than 16 masks for silicon photonics. When a company started looking at monolithic integration they said, ‘To drive these circuits we need very high speed DSPs or drivers. and for that we need 40nm nodes.’ To do photonics in a 40nm process doesn’t make any sense economically.

Attaway: Heterogeneously integrating CMOS with a photonics chip is what makes sense.

De Vries: If you think about the architectural advantages, I have disaggregated what is a common architecture between processor and memory and storage. So that looks like one unit. If I do integrated photonics and some complex SoC-based architecture on two different die, but assemble then in a multi-chip module, I don’t have to pay to change my integrated photonics front end if I want to improve the processor. I have the flexibility to develop all of these different variants and I am not paying for wasted wafer space at 7nm because my SoC and integrated photonics are on the same die. So you are thinking about integration in a different light. The interposer, 3D IC die becomes very attractive, where I can have all of these variants and can integrate the best pieces together.

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