Keeping The Whole Package Cool

Heat dissipation is a critical issue for designers of complex chip-stacking and system-in-package devices. The amount of heat generated by a device increases as the number of transistors goes up, but the ability to dissipate the heat depends on the package surface area.

Because the goal of 3D packaging is to squeeze more transistors into less overall space, new heat dissipation issues are emerging as system-in-package devices become more complex.

Stephen Pan and of  Ansys explained that the temperature of any wire in an integrated circuit depends on three factors. The first, usually dominant, component is the heat generated by the CMOS transistors themselves. This may be the easiest component to predict, and is considered in standard circuit design models.

The second factor is the environment in which the device is operating. Generally speaking, mobile devices operate in less well-controlled environments than conventional desktop computers. Compare a pocket or purse in direct sunlight to a well-ventilated plastic case in an air-conditioned office.

The emergence of “” applications brings new environmental concerns as well, although often the high-performance elements of such systems can be placed in more controlled locations.

Finally, current flowing in the wires within the device leads to joule heating, both in the current-carrying wires and in those closely coupled to them. As the temperature of a wire increases, moreover, so does the resistance, which can lead to further heating.

Thermal flow is not an electrical circuit
But where does the heat go? In single-device packages, it is transported from the active layer, through the interconnect network, and out through the package wiring to the circuit board. Chips that generate unusual amounts of heat, such as microprocessors, often use an auxiliary heat sink attached directly to the package surface.

It’s important to remember, though, that this heat flow is largely uncontrolled. While the electrical circuit is a complex network of precisely defined binary logic, thermal transport is not bound by that design. Heat follows thermal gradients along the path of least resistance — usually the copper wiring — whether a particular wire is carrying current or not.

As King-Ning Tu, distinguished professor in UCLA’s Department of Materials Science and Engineering, explained (paper EP12.3.1) at this year’s Materials Research Society Spring Meeting in Phoenix, AZ, the non-directed nature of heat transfer can have surprising consequences as packages become more complex. For example, a 2.5D package generally uses a silicon interposer with an array of through-silicon vias (TSVs) as a substrate. Individual dies are tiled side by side on the interposer, with fan-out wiring connecting solder bumps to TSVs. It is well-known that if the current density in the fan-out wiring exceeds the electromigration limit, reliability will be poor. Moderate increases in the thickness of wiring traces are generally enough to solve the problem.

Heat dissipation is another matter, however. Some of the heat will dissipate through the solder bumps and TSVs, with consequences that will be discussed in the next articles in this series.

But remember, the heat flow is not controlled. If Die 1, a warm-running logic chip, is adjacent to Die 2, a relatively cool memory chip, then heat can flow down the thermal gradient from Die 1, through the interposer, and into Die 2. Especially during testing and burn-in, when Die 2 is under unusual stress anyway, this excess heating can contribute to thermal migration and, ultimately, device failure.

Managing thermal migration within a complex package is especially challenging because it tends to fall between different areas of design responsibility. The designers of Die 1 have presumably accounted for electromigration within their own design, and expect the package to dissipate the heat they generate. The designers of Die 2 expect the package to provide a thermal environment within their design specifications. It thus falls to the system and package designers to manage the interaction between the two dice, but they won’t necessarily have access to detailed thermal models of either design.

Designing for thermal migration
Appropriate modeling tools do exist. Ansys vice president Norman Chang explained that package designers can analyze thermal flows without having to individually model billions of transistors and wires or thousands of individual TSVs.

However, Jesse Galloway, Amkor’s vice president of advanced package engineering observed that the designer of the interposer needs to be well versed in electromigration issues and have clear design constraints for the current limits and other interposer requirements. System-in-package designs are relatively new, he said, but the drive for increased device density is pushing more designers in this direction. While electro- and thermo-migration analyses are now done on an as-needed basis, he expects them to become a routine part of the design process in the future.

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