LAB Flip Chip Reflow Process Robustness Prediction By Thermal Simulation

By Gabriel Chang and Ricky Zang

Nowadays, there are many interconnects in IC chips. One of the packaging goals is to connect an IC to the next level of subsystem circuitry (package substrates/print circuit boards). Mass reflow (MR) of solder joints is a widely adapted and stable process in the industry. The applications of MR include flip chip, ball mounting, surface mount technology (SMT), and even reliability tests. SMT reflow ovens contain 8 to 20 heating zones and can be used for inline production. However, not only the silicon solder joints but the entire packages inside reflow ovens are heating up during the MR process. This thermal budget will increase package warpage and affect solder joint quality in fine pitch (i.e., less than 60 µm) conditions. Thermal compression with non-conductive paste (TCNCP) and laser assisted bonding (LAB) were introduced to address fine pitch devices with localized heating to reduce package warpage.

In the thermal compression process, the bond head directly heats up the die during the TCNCP process to join the solder with substrate to form the interconnection. The result produces better solder joint quality, lower package warpage and low k layer stress can also be reduced compared to the conventional MR [1-2]. More recently, LAB uses a laser beam as a thermal energy source to focus solder reflow on the die area [3-5], as shown in figure 1.

Fig. 1: Typical lab process.

Compared to the traditional MR, LAB with localized heating provides several advantages in flip chip assembly. The first step is fluxing. The attach head sucks the die into the flux tray and gently dips some flux on the solder joints. The attach head aligns the pad position of the substrate on the stage. Then, the attach head moves down with a certain bond force. The stage will transfer the package to the bottom of the optical module and preheat if necessary. After the laser alignment with the die area, the laser beam will heat up in a few seconds (usually less than two seconds). The emission time depends on many factors. A standardized process or best-known method (BKM) for laser power and duration currently does not exist.

According to the previous research [3], part of the laser beam will be reflected from the surface of the material. In this study, the optimization method was used to find the absorption rate of die by infrared (IR) imaging. Figure 2 (A) shows an example of an IR image on the LAB machine. This IR image provides information on temperature distribution and the hot spot temperature at the top surface of the die. Generally, there are three zones: the center zone is the die area, the middle zone is laser-exposed area, and the outer zone is the area without laser exposure. The uneven temperature distribution of the middle zone implies that the trace layout design should be considered in the simulation model. Figure 2 (B) shows the transient result of thermal simulation with detailed trace layout. The temperature distribution matches the experiment. The absorption rate was correlated under different devices and scenarios.

Fig. 2: (A) An example IR image in the LAB process; (B) The transient results of thermal simulation with detailed trace layout.

Modeling method

A commercial system thermal simulation software, Icepak, is used to build the transient thermal model of packages. Figure 3 (A) shows the model including a flip chip package, solder bumps and substrates in an open and still-air environment. The detailed trace layout and bump distribution of the packages are imported into the model. The environmental temperature is assumed to be 25°C. The bottom side of the substrate is assumed to be at a uniform temperature, 100°C, as is the heat setting, which is the base part temperature of the LAB machine. A heat flux is applied on the die surface and part of the substrate to represent the laser beam. According to the previous research, parts of the laser beam will be reflected from the surface of the material. In this study, an optimization method was utilized to find the absorption rate of die by IR images and then correlate out the expression of absorption rate under different scenarios. To fit the instant temperature of IR images, series transient thermal simulation with the detailed trace were carried out.

Fig. 3: (A) Transient model with detailed trace layout imported; (B) Compact model of consigned substrates.

In some circumstances, the copper (Cu) pattern and Cu via of the substrate is not released due to intellectual property (IP) protection. The generic substrate without Cu pattern and Cu via pose challenges to meet the experimental response of LAB process. To overcome the challenges, an equivalent via block is introduced into the compact model in figure 3 (B). The size of the block is set to be the same as the die and the thickness of the block is the same as the substrate. The material of the generic substrate is assumed to be FR4. The copper residual ratios of the outer and inner layer are 70% and 90%, respectively. The normal direction thermal conductivity of the via block is determined experimentally while the planar thermal conductivity of the via block is the same as that of the compact substrate.

Experimental work

In the LAB process, three key parameters are the machine-power, emission time and beam size. The beam size is defined as slightly larger than the die size to ensure the exposure area of the laser beam covers the die within the shift tolerance of the base jig. The design of experiments (DOE) of power, emission time and related solder joint quality are listed in table 1. Four packages are involved in this work. The Cu Pattern and Cu via of the substrates in Package-C and Package-D are black boxed, which means the design detail of the Cu Pattern and Cu via location are unknown. The peak temperature of the die surface is extracted from the IR image of the machine. The IR images of Package-A and Package-B are utilized first to correlate the emission rate. Then the experimental data of Package-C and Package-D are used to find the expression of the equivalent thermal conductivity of the via blocks.

Table 1: DOE plan of experiments.

Model correlation and verification

Referring to table 2, the power density of the laser beam (Power over Beam size) that in the simulation model is lower than the experimental inputs. The ratio of “Simulated Power Density” over “Power Density” is “Absorption.” From the data analysis, the power density required in the simulation is related to not only power itself but also the emission time and the substrate area directly exposed to laser beams. By optimizing the absorption value in each leg with transient thermal simulation, the best fit absorption value can be found. The absorption is further expressed as follow:

(1)     Ab=0.6235 + 0.0745 t – 0.000313 b – 0.0575 P

where Ab is the absorption of die, t is the emission time, b is the beam area of the substrates, and P is the power density (in W/mm²). Using the correlation equation (1), the relative error of maximum die temperature in the model with detailed trace layout is about 5%.

Table 2: Result of absorption correlation.

With no Cu pattern and Cu via in the black boxed substrates of Package-C and Package-D, the expression of the equivalent thermal conductivity of the thermal block is found through the above method. By optimizing the via conductivity value in each leg with transient thermal simulation, the best fit via conductivity value can be found. Figure 4 shows the via conductivity is highly correlated with bump density.

Fig. 4: Result of the via conductivity correlation.

For the black boxed substrates, the error margin of maximum die temperature is expected to be within 7%, as shown in table 3.

Table 3: The error margin of the compact model.

Applications

To form solder joints in fine pitch devices with the LAB process, a proper temperature range of solder should be granted to ensure that the solder melts properly. If the solder temperature is too low, the solder will not melt properly and result in an open solder joint. If the solder temperature is too high, the solder joints may overflow to result in shorts between solder interconnects. Currently, the solder joint quality is examined by X-ray after assembly, as shown in table 4.

Table 4: The inspection results of Package-A.

Combining the simulated minimum solder temperature in the thermal model and X-ray inspection data, figure 5 shows the allowable range of minimum solder temperature for LAB parameter setup should be between 243°C and 276°C. One can simulate LAB parameters of new packages by this transient thermal simulation to ensure that the minimum solder temperature falls in the proper range before experiments. This work established the ideal index of minimum solder temperature range for the LAB parameter setup of future new packages.

Fig. 5: Allowable minimum solder temperature range during LAB process.

The other application of this method is coupling with mechanical simulation. After laser heating, the solder is melted and then cools down in the air. It will solidify again when the temperature is below 188°C. Referring to figure 6 (A), before this method was developed, one could only assume the temperature near die was uniform and outside volume was uniform at room temperature. However, the analysis shows the simulated stress low k layer is underestimated. With the method described in this article, the temperature distribution of real packages is imported into a quarter finite element model of Package-A to evaluate the low k layer stress due to thermal mismatch between the die and the substrate. Through this method, the LAB parameters stress effect on the low k layer is established by thermomechanical coupling.

Fig. 6: (a) Low k stress result from the uniform temperature assumptions; (B) Low k stress result from the thermomechanical coupling.

Conclusion

This work developed a model with detailed Cu Pattern and Cu via that can simulate results of the temperature distribution in the chip area and the distribution on substrate matching the IR image. From the data analysis, the power density required in the simulation is related to not only the power itself but also to the emission time and the substrate area directly exposed to the laser beams. To predict the LAB parameters for a black box substrate, this study proposes a compact substrate structure that can be used in the LAB process setting without having actual substrate Cu Pattern and Cu via structure. Without the actual substrate Cu pattern and Cu via structure of the substrate, the error margin for the maximum die temperature is expected to increase from within 5% to within 7%.

From the current inspection data, the ideal solder temperature range (above 243°C and below 276°C) is established for the laser parameters setup of a future New Product Introduction (NPI). This work provides a methodology that: a.) can predict localized die temperature using the LAB process, b.) can define the index of solder joint conditions, c.) establishes LAB power and emission time prediction capabilities and d.) evaluates mechanical stress with localized heating distribution effects.

Acknowledgment

The authors would like to thank Amkor factory personnel for help building the test vehicles and conduct experiments. The discussion and help from Hydemanes Wu and Hank Lee for the process details are also appreciated.

References

[1]    Y. Jung et al., “Development of large die fine pitch flip chip BGA using TCNCP technology,” in 2012 IEEE 62nd Electronic Components and Technology Conference, May 2012, pp. 439–443.

[2]    DongSu Ryu, “Advanced Interconnect with Laser Assisted Bonding,” in 2015 SEMICON Taiwan, Sep. 2015.

[3]    Y. M. Jang, Y. Kim, and S.-H. Choa, “Development and optimization of the laser-assisted bonding process for a flip chip package,” Microsyst Technol, vol. 26, no. 3, pp. 1043–1054, Mar. 2020.

[4]    Y. Jung et al., “Development of Next Generation Flip Chip Interconnection Technology Using Homogenized Laser-Assisted Bonding,” in 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), May 2016, pp. 88–94. doi: 10.1109/ECTC.2016.76.

[5]    M. Gim, C. Kim, S. Na, D. Ryu, K. Park, and J. Kim, “High-Performance Flip Chip Bonding Mechanism Study with Laser Assisted Bonding,” in 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Jun. 2020, pp. 1025–1030.

Ricky Zang is a senior director, Advise Analyst, at Amkor Technology Taiwan.