Layers Of Business And Tech Issues

There is no shortage of choices, but which ones will actually work?


Slice an onion in half and one onion pretty much looks like any other onion. Peel it back, layer by layer, and put it under a powerful microscope, and each layer suddenly looks very different.

The same is true for semiconductors. To the outside world, a chip is a chip and an interconnect is an interconnect. Each one has different specs, but even the parts that make up those chips look remarkably similar. Where the similarities end is how those parts are packaged, the material composition, how they’re connected together, the thickness of the wires, the insulation materials, and how much it costs to get a leading-edge SoC into the hands of system makers.

These are complex business formulas based on complex technology and a whole slew of unknowns—consumer demand, market windows, competitive advancements—as well as how new technologies will fare. EUV is a well-known example. It was supposed to be commercially viable at 45nm. It still isn’t ready, and may not be even for 10nm—at least not for all the layers in an SoC. Quadruple patterning may or may not be a replacement or a supplement. It’s never been tried.

This is the same story in almost every part of chip design through manufacturing these days. FinFETs are a proven way to reduce leakage at the gate, which in turn allows chipmakers to turn up the clock frequency. But so far only one company—Intel—is in commercial production, and that’s being done with single patterning at 22nm. What happens with multi-patterning plus finFETs? Test chips show it’s feasible, but that’s about as far as the industry has progressed. No one has a production-ready 16nm or 14nm finFET yet. How much will it add to the cost? What will the yield be? And how many defects will there be per wafer.

More important for many companies, are there alternatives? FinFETs appears to provide a one-time gain in power and/or performance. Fully depleted silicon on insulator provides another. Put them both together, and you may be able to get performance and power gains for yet another node, which is a big deal at 14nm and 10nm. But there are other ways to look at this from a business and technology standpoint. New materials can provide better insulation and buy additional time, particularly with increasing power densities. Better throughput through architectural changes—faster interconnects, different memory configurations, faster I/O and stacked die—can provide still others.

Intel already has gone public with its short-term path, but it’s clearly not the only path under consideration—even Intel is looking at a number of other options. What’s under scrutiny is how all of those options work together—or individually—for a complex supply chain that includes everything from memory to materials to equipment to foundry processes to the available tools for building and testing these complex systems on chip. And just because one vendor takes a particular path doesn’t mean it’s the best approach for other companies.

The challenge is that each of the changes at advanced nodes is getting much more costly than in the past, which means even more scrutiny than ever before by chipmakers, equipment companies, foundries and tools vendors. This may explain why it seems to be taking longer to make decisions than anytime in recent memory. There’s a lot more to see under a big microscope, and a lot more to analyze inside the onion.

—Ed Sperling