Legacy Process Nodes Going Strong

While all eyes tend to focus on the leading-edge silicon nodes, many mature nodes continue to enjoy robust manufacturing demand.

Successive nodes stopped reducing die cost at around the 20nm node. “In the finFET era of processes, esoteric process requirements necessary to move technology forward with each generation have added significant cost and complexity,” explained Andrew Appleby, principal product manager for logic libraries IP in Synopsys’ Solutions Group. “This has created strong transition points between each node.”

From then on, any die shrinks are countered by more expensive processing, and those costs have ramped up dramatically. Mask sets are more expensive, and advanced nodes typically require more layers and therefore more mask sets.

Most foundries and integrated device manufacturers (IDMs) have robust business on older nodes. “Pick your IDM, other than Intel or the memory ones, and many still fab at 130nm and above,” said David Park, vice president of marketing at Tignis. “There is just no need for certain parts to be made at a smaller node.”

Advanced nodes also have fewer customers because not many companies can afford them. “At 3nm there are only 2 or 3 customers,” observed Michael Cy Wang, associate vice president of corporate marketing at UMC. “At 7 nm, maybe there are 5 to 10 customers. But when you come to the 22 or 28nm node, we’re talking about dozens of customers, or more.”

The target design determines which companies can move to advanced nodes and which can’t. “The choice of process node is application-dependent, and some applications won’t move to nodes that require extreme ultraviolet (EUV) technology in the near future,” said Krishna Balachandran, senior director of product management for NVM IP in Synopsys’ Solutions Group. “This is because of the large amount of analog circuitry that doesn’t benefit from scaling, and the absence of requirements to operate at lower power or increase performance. Wafer prices are an order of magnitude lower on mature nodes, and the cost of design and masks are multiple orders of magnitude smaller in mature nodes.”

Disruptions are the rule
Reducing cost with each node used to be easy. “Historically, for process nodes even back before 1µm and down to the 28nm node, the cost of a manufacturing process per wafer always increased per node by about 25% to 30%,” said Kevin Lucas, senior architect, applications engineering, silicon technology group at Synopsys. “However, the number of die per wafer increased around 50%, so the manufacturing cost per die decreased about 20% to 25% per node.” Companies could even take advantage of optical shrinks that required little engineering effort. This was the classical scaling era when Moore’s Law reigned supreme.

Back then, a new node might involve some new process element that added some expense compared with the prior node. But with more chips per wafer, the net cost per die came down. That changed at around the 20nm process node. New nodes resulted in higher performance and/or lower power, but the cessation of cost reduction has meant that moving to the latest node is no longer automatic. “There may be no incremental market value to porting the design to a newer or smaller process node,” noted Park.

The discussion of what’s happened at each node includes some fuzziness. Node names are confusing, and companies don’t always agree on what “nanometer” level a given node is. In addition, the number assigned to the node no longer reflects actual gate length in the way it once did. Changes such as the use of high‑k metal gates altered the fundamental point of comparison, allowing larger features to perform as if they were smaller. The node naming uses numbers as if some of those big disruptions had never happened, and today the names really have no meaning other than as a label for the node. In addition, different fabs make some process changes, such as finFET implementation, at different nodes.

Increased costs for new nodes come from many directions. There may be additional steps (particularly with lithography), new materials, and there almost always will be new equipment. “The leading-edge fabs will incur a premium because they have to recoup their huge CapEx and R&D cost,” said Wang. “Then, of course, they need to justify their premium when they sell downstream.”

A benefit of older processes is the ability to employ legacy equipment. “There are many companies still making parts on the same equipment from 20+ years ago,” noted Park. “The fabs and equipment are long depreciated, so they are literally printing money with every chip they make.”

Tracing the nodes
Silicon processes have evolved from the micron level to the nanometer level. But the big process disruptions have happened at the tail end of that history. Some of the biggest changes have been:

• Somewhere between 130nm and 90nm, wafers went from 200 mm (8”) to 300 mm (12”). A 300mm wafer is more expensive than a 200mm wafer, but you spread that cost over many more chips for lower net die cost.
• Around 45nm, features were small enough that computational lithography was necessary to nudge light into printing the features cleanly.
• At around the same time, high‑k dielectrics with metal gates came into use, preventing gate oxide thicknesses from getting too thin.
• At 30nm for NAND flash and 20nm for digital logic, multi-patterning using 193nm immersion technology became necessary because EUV lithography (13.5nm) was not ready for production. Double patterning (and later quadruple patterning) significantly increased manufacturing cost, but it was the only way to print smaller features.
• At 22nm, finFETs were first adopted. They went mainstream at 14nm.
• EUV started at 7nm and was required at 5nm.
• At around 5nm, multi-patterning with EUV started.
• The 14-angstrom (Å) node may first start using high-numerical-aperture (high‑NA) EUV.

Fig. 1: Changes in silicon processing. Larger wafers, high‑k metal gates, computational lithography, and multi-patterning added processing cost, but they were necessary for performance, power, and (originally) cost. But at around 20nm, die cost started increasing. Extreme UV (EUV) and its high numerical-aperture (NA) version are yet more expensive, as are gate-all-around (GAA) transistors. (Source: Bryon Moyer/Semiconductor Engineering)

The change in economics has caused something of a split in the industry. Some companies and products chase whatever process gives the highest performance (or lower power) at any time, and their products have pricing that can support the higher costs at each node. Companies such as Intel, Samsung, and NVIDIA are in that enviable position. Everyone else must stick to the older nodes because they can’t command the same prices. Some chips sell for 20 to 30 cents.

That leaves some process nodes, such as 10 or 7nm, with the prospect that design starts will drop, because they’re no longer the fastest. But they’re still too expensive for many of the more prosaic chips being built. That suggests that many designs will pile up on older nodes rather than moving forward. The highest-performance chips, meanwhile, will follow the fastest node they can, leaving a hollow for the high-performance has-been nodes.

Successive nodes are more expensive to produce, and they’re also more expensive to design. “When a design house decides on the process node, they need to consider not just the cost of the wafers and masks, but the cost of design and its impact on time to market,” said Al Blais, principal, product management, in Synopsys’ EDA Group. “Process nodes that include double patterning require additional design and IP complexity. FinFET designs have additional design restrictions, as does EUV. High‑NA EUV will absolutely have new requirements.”

UMC’s Wang agreed. “Going to the leading edge right now is maybe $3 million to $5 million at 5 or 7nm for a mask set,” he said. “But the design cost, if you add up all the design engineering and IP cost over the duration of the project, is easily tens of millions of dollars.”

Different nodes, different apps
Companies manufacturing leading-edge chips often attribute increasing demand to the growth in AI applications which depend on CPUs, GPUs, or dedicated neural-processing chips. Less in the headlines are applications such as smartphone application processors, high-performance computing (HPC), and server chips for the cloud.

The nodes on which these products are built are most vulnerable when the next generation is implemented. “The key customers of leading applications are ready to move on to the next bleeding-edge node, and then there will be a loading void for the fabs, especially when the volume is high,” said Wang.

But far more chips are built on older nodes. For example, there is increasing demand for power management ICs (PMICs) for electric vehicles. “PMICs typically use mature nodes like 180nm or 130nm, but on a BCD process (bipolar, CMOS, D-MOS),” said Balachandran. “PMICs are getting smarter, incorporating increasing amounts of digital logic along with analog circuitry. Consequently, designs are moving to 90nm, 55nm and 40nm BCD process nodes.”

Sensors, meanwhile, are farther back on the 180 and 150nm nodes. “For automotive applications requiring tolerance to high voltages, they’re integrated with other analog circuits on a BCD process – again predominantly in 180nm or 130nm,” Balachandran said. “Advanced smart sensors incorporate microcontrollers and are moving to 65nm or 40nm, but that is state of the art for these applications. Top-of-the-line CMOS image sensors use a 22nm low-power process and are migrating to 12nm finFET processes.”

Process nodes are often application- and use-case specific. “Chips for use in IoT systems represent some of the bifurcation in targeted process nodes,” Balachandran said. “For cost reasons, they’re mostly staying at nodes like 40 and 22nm.” But as AI moves to the edge, more devices will have some inference capabilities, and the chips performing that function will need higher performance than the rest of the digital logic, so they’re moving to 6nm, according to Balachandran.

Analog and mixed-signal chips also tend to stay behind. “If there’s a mixture of analog and digital circuitry for the application, then we see 55nm as the sweet spot,” noted UMC’s Wang. “Pure analog tends to stay at the 8-inch advance nodes – typically 180 and 150nm.”

These older nodes aren’t static either. Some fabs try to inject new life into older processes by making improvements that can attract new designs. “Foundries actively adopt programs to refresh their technology offerings mid-life as nodes fall from the leading edge,” said Synopsys’ Appleby. “This can include the introduction of specific transistor devices for enhancing performance or minimizing leakage, process shrinks for improving costs and tooling utilization, adding specific RF features or high voltage for enabling mixed-signal systems, or adding automotive-grade qualifications.”

The advent of chiplet technology is affecting these choices, as well. In theory, one no longer needs to migrate some capabilities to a more advanced node just to put everything on one chip. Instead, only the parts that truly require the capabilities of an advanced node can move there, minimizing the die size at the expensive node. The remainder can be integrated as separate chiplets within the package.

That packaging, however, is expensive today. “It’s easy to build chiplets using the process node and technology most suitable for each chip type,” said Wang. “Customers would certainly consider moving to chiplets if the economics justified it. But current chiplet solutions are still facing various yield and cost challenges and are not yet cost-effective for many applications.” So even though chiplets can save chip cost, advanced packaging costs must come down to allow a net cost savings.

Keeping the line going
Although some fabs and foundries focus on pushing the limits, others, like UMC, focus on legacy workhorse process nodes. It sees 22/28 nm as its main node. “That’s the last generation on planar technology,” observed Wang. “Moving to finFETs adds significantly to the manufacturing cost.”

Meanwhile, some nodes may just wither away. “There’s little adoption of the foundry 10nm node because the performance didn’t justify the cost,” noted Wang. The question that remains is how many new designs will target 7nm now that 5, 3, 2nm, and below are becoming available. Devices that do not require finFET technology, for example, will remain on nodes older than 14 or 12nm. EUV is the next big technology bump, and it will filter even more designs out. Unlike 10nm, 7 and 5nm are likely to persist simply due to existing production. But three years from now, when those production units have been passed over for those on newer nodes, will there be enough new designs to keep that fab line full? If the main barrier to finFETs is cost, it seems ongoing process improvements will be implemented instead.

Conclusion
Given the size of process-migration barriers, it’s likely that the nodes between 12nm and 2nm node will see reduced design starts compared with older nodes. The industry may see a snowplow effect where designs pile up at 28nm, for example, and resist the temptation to jump further in lieu of a compelling benefit.

“Technologies at sharp transition points, such as the last generation of planar nodes, are guaranteed a long life because they offer the optimum set of features for many classes of products that don’t need the next node,” said Appleby.

Meanwhile, companies using mature technology are still doing quite well. “Microchip is an example of a company that is still successfully leveraging older nodes,” observed Park. “They shipped over 8 billion devices last year from two 8-inch and one 6-inch fab at process nodes from 0.13µm to 1µm. And they have been profitable every quarter for 32 years. They are just one of many semiconductor companies profitably manufacturing at older nodes.”