Let’s All Meet At The Via Bar!

By Jean-Marie Brunet
At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increase in the use of vias, but also led to an escalation in the number and complexity of design rules that define how vias are selected and placed in a layout. Place and route (P&R) issues for advanced node designs are becoming significantly more challenging, and our current methods of chip layout and verification are starting to fall short.

Via failure always has been a significant yield detractor. Via redundancy (in the form of double vias) was introduced into the layout process at 65 nm to help reduce the number of via failures caused by manufacturing variability. At 28 nm, we’ve added a rectangular via (sometimes called a Via Bar). Replacing single vias with rectangular vias, rather than the double via, retains the protection against via failure while reducing the overall via count. Figure 1 illustrates the three via types.

Figure 1. Types of via connections are expanding.

Reducing the via count is important, because the number of traditional vias required for designs at 28 nm and below has significantly increased, primarily due to two new factors. One, there are simply many more metal layers at 28nm and below, requiring many more connections. Two, new types of design requirements have emerged at these design nodes. For example, double-patterned layers may increase the number of vias needed due to the necessity of decomposing geometries, while electromigration constraints are driving requirements for more and different types of vias on the power and ground topology.

Along with the increase in the number of vias, even more dramatic is the rise in the number and complexity of the rules needed to ensure the proper placement and selection of vias during P&R. There are four primary reasons why the complexity of via insertion is rising so quickly:

1. In a smaller design, connections are more challenging, requiring new configurations not typically used at larger nodes, and consideration of factors that were previously not significant. For example, at 20 nm, via selection requires an evaluation of both the metal end -1 and the metal end +1. The router doesn’t just optimize the via by itself anymore, but in combination with the metal above and below, as well as the via’s orientation to that metal.
2. More via types to choose from increase the via options a router can use. More routing rules are needed to define when and how a particular type of via should be used.
3. Foundry rules for via priority—each foundry has its own proprietary rules for selecting a particular via type. While a routing rule may allow the router to choose among multiple via types, the foundry priority rules govern the order in which these types must be considered, depending on geometry, surrounding characteristics, via enclosure, and a host of other variables. Additionally, these priorities may shift rapidly during the development of a process node, requiring frequent updates to the router.
4. Double patterning—double patterning decomposition requirements influence the placement and orientation of vias, and must be considered at the P&R stage.

But why is all this a problem? Don’t routers have routing rules that tell the router how and where to place elements of a layout?

In the digital world, detailed routing design rules are often approximated by simplified rules that can be coded into the Library Exchange Format (LEF) specification or router technology file (tech file). Typically, a router uses these simplified DRC and DFM rules to provide the optimal trade-off between runtime and accuracy during routing. Once the implementation is complete, the GDSII layout is verified using signoff-quality DRC/DFM models and Standard Verification Rule Format (SVRF) rule decks. For previous nodes, this worked adequately because the number of violations discovered at signoff was relatively low.

As a new process node matures, the foundry’s design rule files, expressed in the SVRF language used by signoff engines, are constantly updated to address manufacturing issues as they are discovered. Consequently, these foundry signoff models and decks are intrinsically the most accurate and complete representation of actual manufacturing requirements. The rules used by the P&R tool, expressed in the LEF/tech files, are simpler, and frequently fall out of sync with the foundry rules.

Further, at 28 nm and below, there are some rules that simply cannot be expressed in the simpler LEF/tech file language. As a result, the router will report a layout to be DRC/DFM clean, but signoff analysis finds a large number of violations. Not only is debugging and correcting these errors after P&R time-consuming and resource-intensive, but the changes made to fix them can lead to new manufacturing violations, or negatively impact the performance targets of the design.

At 28 nm and below, the rules that govern via selection and placement have exploded off the charts (Figure 2). Not only are there more rules, but the rules themselves are more complex. As discussed, there are now multiple types of vias to choose from, depending on the local environment, and each foundry has its own preferred ranking that determines how a via type is selected. Additionally, via placement may be affected by other design factors, such as double patterning.

Figure 2. Routers are being challenged by the growth in via rules and their complexity.

These new process requirements associated with via selection are not only numerous, but also complex in implementation. If you are using a rectangular via, how do you place an array of vias? How do you accurately determine via enclosures when accounting for double patterning requirements? The LEF/tech file must not only be able to understand and account for these conditions, but it must also be able to understand and apply a particular foundry’s requirements for priority, selection sequence, orientation, and enclosure. Each time a router places a via, it must determine the layout options, then go through that foundry’s priority sequence to determine the correct via selection and placement. And, as previously discussed, these priorities may frequently change, requiring ongoing router updating.

So, what are designers to do? Even if you take the P&R system as far as you can, using the LEF/tech file to complete roughly 80% of the via placements in layout that you can achieve with your router, you’ll still be missing about 20% of what you need to do to optimize via selection and placement. Of course, just like you learned in school, that 20% usually will be the hardest and most challenging via optimizations, and will carry the greatest likelihood of generating yield impacts. While there are foundry-certified utilities to help you successfully debug and correct these via issues, how much time and energy will it take to accurately back-annotate the Design Layout File (DEF) with these corrections?

But there is hope. Recent technology advances have made it feasible to use these foundry-certified utilities to not only automatically fix these complex via placements so they are DRC/DFM-compliant, but also to automatically back-annotate these changes in the original P&R DEF. In the near future, it should be possible for designers to ensure that 100% of the via optimizations required in a design can be addressed efficiently, accurately, and quickly during the P&R phase of the design flow.