Manufacturing Bits: June 3

World’s thinnest TFTs
The U.S. Department of Energy’s Argonne National Laboratory has devised the world’s thinnest flexible, 2D thin-film transistors (TFTs). The transistors are just 10 atomic layers thick.

TFTs are typically used in screens and displays. In the lab, Argonne researchers fabricated the TFTs on both a conventional silicon platform and a flexible substrate.

Scientists from Argonne created the world’s thinnest flexible, transparent thin-film transistor. (Source: Argonne)

Monolayer graphene was used as the metal electrodes. Three to four atomic layers of h-BN (boron nitride) were used as the gate dielectric. And bilayers of WSe2 (tungsten diselenide) were used as the semiconducting channel material for the TFTs. “We chose tungsten diselenide because it provides the electron and hole conduction necessary for making transistors with logic gates and other p-n junction devices,” said Argonne scientist Anirudha Sumant, on the agency’s Web site.

The field effect carrier mobility was 45 cm2/(Vs), according to researchers. This exceeds the mobility values of today’s TFTs by 100 times.

The active device stack of WSe2–hBN–graphene was found to be more than 88% transparent. The device characteristics were unaltered for in-plane mechanical strain of up to 2%, according to researchers. The device demonstrated temperature stability over 77–400 K. Low contact resistance value of 1.4 kΩ-μm and sub-threshold slope of 90 mv/decade were reported.

“We were pleased to find that the on/off ratio is just as good as current commercial thin-film transistors,” said Argonne postdoctoral scientist Saptarshi Das, “but the mobility is a hundred times better than what’s on the market today.”

Self-formed barriers for interconnects
The interconnect remains a challenge in next-generation designs. The metallization step is key in the interconnect flow. For years, a thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials have been deposited using physical vapor deposition (PVD).

Ta is used to form the liner and TaN is for the barrier in a structure. Recently, Applied Materials rolled out a tool, which enables cobalt films for the liner. CVD-based cobalt liners improve the overall copper fill.

What’s next? At the recent IEEE Joint Conference of the International Interconnect Technology Conference (IITC), Applied Materials and Imec described a CVD process, which enables manganese-based self-formed barriers (SFB).

The Mn-based SFBs were compared to conventional PVD-based barriers at 40nm and 100nm half-pitch. In the lab, Mn-based SFBs led to both maximum fractional copper areas in the trenches and copper resistivity reduction at scaled dimensions, which, in turn, represents a breakthrough for future interconnect scaling.

Mn-based SFBs were deposited using Applied’s 300mm Endura platform. A thickness of Mn-based SFB was targeted at about 2nm, according to researchers. PVD-based copper was deposited on the same platform.

“Compared to TaNTa, Mn-based SFB offers maximum fractional Cu area in the narrow trenches,” according to the paper at IITC. “A plot of Cu resistivity as a function of Cu area confirmed 14% lower Cu resistivity using Mn-based SFB. Finally, promising TDDB and EM reliability results have been demonstrated in 20nm HP SD SiO2 trenches integrated with Mn-based SFB. All these results make Mn-based SFB a promising candidate for future interconnect scaling.”

Litho sailing
Directed self-assembly (DSA) is generating steam in the industry. In DSA, block copolymers (BCPs) are used for the fabrication of periodic structures with length scales below 100nm.

Researchers at the Institut Català de Nanociència i Nanotecnologia (ICN2) have developed a new method to produce hexagonal periodic arrays with high fidelity in a timely and cost-effective manner. This technique combines nanoimprint lithography with DSA.

“Directed self-assembly of block copolymer polystyrene-b-polyethylene oxide (PS-b-PEO) thin film was achieved by a one-pot methodology of solvent vapor assisted nanoimprint lithography (SAIL),” according to researchers.

Using SAIL, simultaneous solvent-anneal and imprinting of a PS-b-PEO thin film on silicon without surface pre-treatments yielded a 250nm line grating decorated with 20nm diameter nanodots array, according to researchers.

The periodicity of the copolymer was 40nm. The order of the hexagonally arranged nanodot lattice was quantified by SEM image analysis. “The imprint-based SAIL methodology thus demonstrated an improvement in ordering of the nanodot lattice of up to 50%, and allows significant time and cost reduction in the processing of these structures,” according to researchers.