Marching Orders

The feature shrink will continue for all chips, but not necessarily for everything that’s used in those chips.


Reports back from the front lines of Moore’s Law are rather consistent—14nm and 16nm finFETs are do-able, but they’re not easy to design, verify or manufacture. In fact, the only high-volume source of production-proven finFETs at this point is Intel, which is turning them out at 22nm.

A number of issues are cropping up at the most advanced nodes, and while each is ultimately solvable, together they raise the overall complexity and cost of the designs—while also providing glimpses into potential shortcuts and impetus for different approaches.

First of all, the 14nm and 16nm finFET processes from GlobalFoundries and TSMC, respectively, are based on a 20nm back-end-of-line process. Double patterning is well understood and tested at this process node, and there is plenty of experience in stitching together dual color schemes or ignoring everything until it reaches verification.

The same can’t be said for triple or quadruple patterning, which will be required with 14/16nm BEOL processes. It’s bad enough to have to design in red and blue. Now there will be three or four colors, and the amount of stitching required will be multiples higher. This isn’t a one-plus-one type of approach, because stitching creates its own set of problems, and the more stitches that are required the more it can impact the overall integrity of the design.

FinFETs can help in a couple of ways. First of all, because dynamic and static leakage are lower, the clock speed can be increased to achieve better performance in the same area with a less-dense configuration, which in turn eliminates some of the physical effects issues. Alternatively, finFETs can be used to maintain the same performance in a smaller area. But doubling the number of transistors in the same area while also increasing the clock speed will add new problems, such as thermal differences up and down the 3D transistors and an overall increased power density that is becoming a thornier problem every feature shrink. FinFETs can be clocked higher than 2D chips because of the reduction in leakage, allowing companies to boost performance in the same or smaller space, but the dynamic power density will still increase.

A second issue, and one that is closely related, is what will happen on the lithography front. Ask industry executives about the fate of EUV and the answers vary from a shoulder shrug to an embarrassed look. After all, it was supposed to be ready at 45nm for sure, and maybe even at 65nm. Directed self-assembly seems to be making some process as an alternative, and so are e-beam and X-ray lithography. But progress is a relative term. EUV has made progress, too, and it still isn’t commercially viable, which is why companies are now looking at the impact of triple and quadruple patterning. Without a lithography breakthrough, multipatterning is a given, and that adds both time and cost to each new wafer.

A third issue involves 450mm wafers. Whether they really will continue to reduce the cost per die is unknown, because that will rely heavily on yield. This kind of economic equation isn’t as simple as it was moving from 200mm to 300mm wafers because it’s not an apples-to-apples comparison. Even with all the equipment needed to handle 450mm wafers, multiple lithography passes, process variation and physical and proximity effects at the most advanced nodes all will affect yield. They also will limit the number of customers who actually can afford to make the move to the latest process nodes and to design chips at the most advanced nodes.

A more likely scenario, and one that is gaining renewed attention even among major chipmakers, is a platform-based approach that relies on tighter integration between the chip and the board. Xilinx’s 2.5D prototype was a first step in that direction, but it now appears the designs will involve more than just four chips connected to an interposer. They will involve many chips, some even stacked vertically, and all connected through an interposer in the middle. This approach, which was panned initially because of cost, is now getting a second very serious look because the cost differential isn’t so significant at advanced nodes, particularly when you factor in verification, test and yield.

Logic most likely will continue to be manufactured using the most advanced digital processes, and so will memories. These technologies use very regular structures, which makes them easier to place, route, verify, test and manufacture. The rest—analog/mixed signal IP, some standard digital IP, and a variety of new entrants such as MEMS and even I/O—don’t exhibit the same economies of scale from feature shrinks. Economies of scale will continue for certain digital functions through at least 7nm and maybe well beyond. But in the future they likely will be part of an overall chip-package-board and IP integration equation, which takes advantage of whatever makes the most sense at any particular time and for any particular market. That will be the only way these advanced digital processes will be used in high enough volume to warrant continued investments in advanced lithography, 450mm wafers and whatever else is required on the tools and equipment side to keep Moore’s Law viable.