Mashup At 7nm

There are much broader implications to the SEMI/ESD Alliance merger than meet the eye.


The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal.

Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no possible way for a chipmaker to keep track of all of the intricacies of a process and the rule decks, which vary from one foundry to the next. That data needs to be built into the design from the start to avoid problems when it reaches manufacturing, generally in the form of GDS II code.

Much has changed over the past several nodes. At 28nm and above, it was still possible to have a working knowledge of all of the design rules. Below 28nm, it’s impossible. There are too many potential interactions and corner cases to track. Doing this manually would result in poor yield, costly re-spins, longer time to market, and more failures in the field.

It wasn’t always this way. When design for manufacturing (DFM) software was first introduced as a concept, somewhere around the 130nm node, many chip companies scoffed at the idea. At 90nm, there were more than a dozen DFM companies, none of them particularly successful. At the time, DFM was referred to as “design for marketing,” and there were a number of other variations introduced around the same concept—design for yield, design for test, design for profitability. In the end, the design industry settled on DFx.

That was then. Fast forward to the latest nodes and EDA since has succeeded in becoming an indispensable component of the manufacturing process. It is essential for multiple patterning, for keeping track of design violations, and generally for keeping chip designers out of known trouble spots. It has become so critical, in fact, that chipmakers have quietly voiced concerns about foundries buying the EDA companies and incorporating those tools into their flows.

Regardless, the working relationship between design and manufacturing grows closer at every node. Large chipmakers, EDA companies, IP companies and foundries all are working together at the most advanced nodes to develop new manufacturing processes and rule decks. It helps that the large EDA companies also sell IP, so they can make sure that tools and IP are ready along with the new processes. And it helps that the foundries are sharing more data at each new node than ever before with the EDA companies. Even Intel Foundry, which has been notoriously private, has begun sharing some of its data, according to multiple sources.

The problem the entire industry is facing is that for manufacturing to be effective, the rules have to move even further left. There has been talk about compressing the front and back end of manufacturing, and there has been much work underway in the EDA sector to begin verification and test much earlier in the design flow, which has been termed “shift left” because it’s based upon a flow diagram of what used to be sequential steps.

What’s changing is the manufacturing planning has started to overlap with the design flow, which represents a much tighter compression. But it’s no longer just a vector. It’s now more of a four-dimensional matrix, in which checks are done at various times and connected upstream and downstream, with various checks in other areas connected at other times.

Looked at from this perspective, the merging of the ESD Alliance with SEMI takes on much more significance. These two worlds have become intertwined over the past couple process nodes, and that relationship is only going to become even tighter at each new node going forward.

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