Memory Directions Uncertain

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are , chief executive officer at Kilopass Technology; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at Synopsys; Scott Jacobson, business development within sales and marketing at Cadence; and Frank Ferro, senior director for product development in the interfaces and memory division of Rambus. What follows are excerpts of that conversation.

In part one, the panelists talked about the bifurcation of memory requirements between mobile and desktop and some of the approaches needed to tackle them.

SE: Does create a difference between the worlds where you can never have enough memory on-chip versus those that would be fully satisfied?

Nandra: It all comes down to economics. Some proposals we are seeing rely on cheaper TSV technology for 3D ICs to become successful. My opinion is a hybrid memory cube (HMC) has more chances because the memory supplier is responsible for the TSV. With high-bandwidth memory it is up to the system guy.

Ferro: When you have a bill of materials, the weakest link is going to affect your yield. In a company I previously worked for that did multi-chip modules (MCM), when one component breaks, the whole thing gets thrown away so the cost goes up. With high-bandwidth memory or HMC you are still looking at applications that require the highest speed and these are not likely to get close to my mobile device any time soon.

SE: For off-chip memory, we have heard that DDR4 may be the end of the road. Is that industry going to stagnate or are their additional opportunities?

Ferro: At Rambus, we have demonstrated a 6.4Gb/S test chip that has been running for about a year. So we know that we can double the current 3.2Gb/S. If that is proposed as a standard in the future, that could take DDR and LPDDR on another round. So we still have a ways to go. It is true that we are not seeing a lot of DDR5 proposals.

Nandra: DDR4 3200 is going to have a long life. Discussions about the death of DDR are extremely premature.

Jacobson: If you look at the history of DDR, and graph out the progression of standards, you see this nice flow where the length of the next technology adoption is a nice step, but suddenly with DDR4 there are a whole bunch of new technologies that are dropped in such as HMC, HBM, Wide I/O2. The path forward is being pressured by this shopping list of technology approaches to solve the memory problem. Bandwidth is driving a whole new view of how to do this. From a customer point of view, when they are constrained, they always manage to do amazing things. When they are constrained by cost, they get very creative. They are saying that if there isn’t anything beyond the next generation of DDR, can I look at one of the new technologies and cut my cost and get the advantage of the architecture of the new technology and get more bandwidth. If they can’t get the right price/performance they will look for another solution.

SE: what about the new technologies for memories themselves – ReRAM, MRAM. How far out are these technologies and what impact will they have?

Cheng: The fundamental latency of DRAM is very slow. The speed for (NVM) is 15-20nS, so about 50MHz. Now ask yourself, why would I want to have a DRAM that runs slower than a disk. NVM has a potential to say get rid of $20B of DRAM and replace it with NVM and re-architect the whole system. But the devil is in the detail which is how do you make this a reality. This is difficult. The semiconductor industry is very different than it was in the early 1980s. Today the manufacturing guys who can experiment with the new memories is very far away. It is very large scale, not conductive to experimentation and the crazy guys here on the West Coast are trying to figure out these things but there is no one to build them. That is slowing down the innovation. But even if a new memory were to come in it would make half of this conversation irrelevant. You would have NVM directly connected to your processors. This would shrink the power consumption enormously. All of the power consumed by DDR and would be gone.

Jacobson: This brings in another element that is facing the industry – security. When you go into an NVM world, there is a whole unaddressed area of the best way to provide security. There are many challenges here.

Cheng: This is not a change. Bringing in NVM eliminates the middle man. It removes the DDR interface. It is difficult to know exactly what it would need to connect the memory to the processor because its behavior is different.

Ferro: DRAM is still the cheapest storage. From a practical standpoint, decisions have always been made from the cost perspective. There are manufacturing challenges with both MRAM and ReRAM. We are asking the same questions. When is ReRAM going to be ready? I agree it is a manufacturing challenge and I do not have a good view of when those will be overcome.

Jacobson: These new technologies are still struggling with a scale issue.

Cheng: This is true for the consumer market, but it is not true for data centers. Data centers are relatively price indifferent.

SE: Some companies in the microcontroller space have already started to ship devices with ReRam in them. It has often been said that this is a natural place to replace NOR flash because of the associated manufacturing costs. These are not attempting to get to the latest nodes – instead being satisfied with 40nm and even 65nm.

Cheng: If it works there, it may well migrate.