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Micron D1α, The Most Advanced Node Yet On DRAM

Digging into the first sub-15nm cell integrated DRAM product.

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Finally, we got to see D1α DRAM generation! It’s 14nm! After a quick viewing of the Micron D1α die (die markings: Z41C) and its cell design, we have determined its actual technology node (design rule), in contrast to the claims of market literature. It is the most advanced technology node ever on DRAM, and it is the first sub-15nm cell integrated DRAM product.

The Micron Z41C die removed from MT40A1G8SA-062E:R (FBGA Code: D8BPJ) is the most advanced 8 Gb DDR4-3200 (data rate = 3200 MT/s) SDRAM with Micron’s D1α technology applied. Micron described it as 40% improvement in density vs. D1z with ~10% driven by design efficiency.


Fig. 1: Micron DRAM Technology Roadmap. Micron extends their D1α volume production in 2021.

Although D1y and D1z DRAM DDR4/LPDDR4/LPDDR5 products are the current market standard, Micron successfully developed and started shipping D1α DRAM chips in 4Q2020, as shown in figure 1. Micron D1α process integration technology, design, and performance have been attracting a lot attention because D1α generation would be the first sub-15nm cell design. Further, Micron’s D1α DRAM products use ArF-i based lithography only, without EUVL photomasks applied, which is quite different from Samsung’s EUVL strategy on DRAM scaling.

D1α die size is 25.41 mm2, and bit density is 0.315 Gb/mm2, which is the industry’s highest DRAM density to date. In comparison, previous D1z DDR4 DRAM dies have 0.299 Gb/mm2 (Samsung 8 Gb Non-EUVL D1z DDR4), 0.247 Gb/mm2 (Micron 16 Gb D1z DDR4), and 0.296 Gb/mm2 (SK Hynix 16 Gb D1z DDR4 C-die), which means Micron has increased bit density by ~28% from the D1z.


Fig. 2: DRAM Cell Size Trend from three big players, Samsung, SK Hynix, and Micron.

From the perspective of the cell size trend shown in figure 2, DRAM cell size has continued to scale down. Blue squares show Samsung’s cell size, and gray circles show Micron’s. Until the D1x generation, there was a bit of a technology gap between Samsung and Micron, where Samsung had led Micron for each generation. However, with the D1y generation, the gap had narrowed, and all of the big three DRAM companies showed the same cell size for the D1z generation.

With D1z, Micron had successfully caught up to Samsung; now, Micron has already introduced their new and most advanced D1α generation products to market. We found and quickly examined Micron D1α generation cell design, and the cell size measured 1,672nm2, which is the smallest cell size on DRAM to date. Its design rule measured 14nm, more specifically 14.4nm, which is the most advanced cell design from the DRAM industry.


Fig. 3: DRAM cell D/R shrink ratio trends from D2x through D1α; Samsung, SK Hynix, and Micron

Micron D1α is the most advanced technology node ever on DRAM, and the first sub-15nm technology node. And Micron achieved it using ArF-i based lithography, which means it’s non-EUVL based, and a very different approach from Samsung’s D1z or D1a. DRAM cell integration keeps 6F2-based cell design for every DRAM foundry. Design rule on DRAM cell sizes are trending smaller from Samsung, SK Hynix, and Micron. Figure 3 shows the trends of shrink factors, D2x through D1z and Micron D1α generation. For example, Micron kept 0.87 for many years, however for their D1z, the shrink factor increases up to 0.92. Samsung and SK Hynix shrink factors increased from generation to generation, and for the D1z generation, it’s higher than 0.92, which means it’s getting harder to shrink DRAM cells. Micron D1α D/R shrink ratio has just been added to this comparison chart with its shrink factor of 0.9. The shrink factors would be kept 0.9~0.92 for a while, such as for D1a (D1α), D1b (D1β) and D1c (D1γ) upon 6F2 BCAT 1T+1C integration.

TechInsights has been digging into the device, including structure, process, materials, transistor characteristics, and circuit analysis. Please stay tuned!



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