How a machine learning model running on the ACS Edge infrastructure improve identification and binning of fail parts compared with conventional statistical screening methods.
IC Test is a critical part of semiconductor manufacturing and proper die binning and material disposition has an important impact on the overall yield and on the process monitoring and failure mode diagnostics. Edge analytics are becoming an increasingly important aspect of die disposition. By intercepting parts in real-time at the wafer test step, we can save downstream processing needs. In this paper we show how a machine learning model running on the ACS Edge infrastructure can provide 20 to 40x improvement in identification and binning of fail parts compared to conventional statistical screening methods. We also show that by incorporating known cost data, we can automatically guide users to optimally tune the model for maximal failure capture with minimal overkill and realize significant business savings.
Published in: 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Date of Conference: 07-10 March 2023
DOI: 10.1109/EDTM55494.2023.10102972
Authors: Tomonori Honda, Thijs Haarhuis, Jeffrey D. David, Henri Hannink, Greg Prewitt, and Vishnu Rajan, all from PDF Solutions, Inc., Santa Clara, Ca, USA.
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