A technical paper titled “TOP: Towards Open & Predictable Heterogeneous SoCs” was published by researchers at University of Bologna, ETH Zurich, and University of California San Diego.
“Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial automation. An effective approach involves the modeling and development of hardware components, such as interconnects and shared memory resources, to evaluate or enforce their deterministic behavior. Unfortunately, these IPs are often closed-source, and these studies are limited to the single modules that must later be integrated with third-party IPs in more complex SoCs, hindering the precision and scope of modeling and compromising the overall predictability. With the coming-of-age of open-source instruction set architectures (RISC-V) and hardware, major opportunities for changing this status quo are emerging. This study introduces an innovative methodology for modeling and analyzing State-of-the-Art (SoA) open-source SoCs for low-power cyber-physical systems. Our approach models and analyzes the entire set of open-source IPs within these SoCs and then provides a comprehensive analysis of the entire architecture. We validate this methodology on a sample heterogenous low-power RISC-V architecture through RTL simulation and FPGA implementation, minimizing pessimism in bounding the service time of transactions crossing the architecture between 28% and 1%, which is considerably lower when compared to similar SoA works.”
Find the technical paper here. Published January 2024 (preprint). GitHub: https://github.com/pulp-platform/soc_model_rt_analysis
Valente, Luca, Francesco Restuccia, Davide Rossi, Ryan Kastner, and Luca Benini. “TOP: Towards Open & Predictable Heterogeneous SoCs.” arXiv preprint arXiv:2401.15639 (2024).
Related Reading
Pinpointing Timing Delays In Complex SoCs
In-circuit monitors become essential to understand the causes of failures over time and under real-world operating conditions.
RISC-V Micro-Architectural Verification
Verifying a processor is much more than making sure the instructions work, but the industry is building from a limited knowledge base and few dedicated tools.
Anatomy Of A System Simulation
Balancing the benefits of a model with the costs associated with that model is tough, but it becomes even trickier when dissimilar models are combined.
Leave a Reply